A semiconductor package method includes: providing a first carrier board, forming a first molding layer covering the upper surface of the first carrier board and the bridge chip after bonding an upper insulation layer of the bridge chip on the upper surface of the first carrier board; thinning the first molding layer and the lower insulation layer, and forming a first redistribution layer on the surfaces of the thinned first molding layer and lower insulation layer, the process for forming the first redistribution layer includes an electroplating process; thinning the upper insulation layer and the first molding layer, forming a second redistribution layer on the surfaces of the thinned upper insulation layer and first molding layer, and the process for forming the second redistribution layer includes an electroplating process; and providing a semiconductor chip, mounting the semiconductor chip on the upper surface of the second redistribution layer, and the semiconductor chip being electrically connected with the second redistribution layer.

An interposer substrate is provided between a mounting substrate and a semiconductor device. The interposer substrate includes a conductor electrically connecting the mounting substrate and the electronic device; a mechanical member electrically insulated from the mounting substrate, the semiconductor device, and the conductor; and a first resin material provided around the conductor and the mechanical member, wherein the mechanical member has a Young's modulus higher than that of the first resin material.

An electronic device includes a first substrate structure, a first circuit structure and a package structure. The first circuit structure is disposed on a surface of the first substrate structure, and the first circuit structure includes a first substructure. The package structure is disposed on the first circuit structure and electrically connected with the first circuit structure. The first substructure has a first coefficient of thermal expansion, the package structure has a second coefficient of thermal expansion, and a ratio of the second coefficient of thermal expansion to the first coefficient of thermal expansion is greater than or equal to 0.8 and less than or equal to 1.5.

A semiconductor package may include: a first wiring structure including a first wiring pattern and a first wiring insulating layer surrounding the first wiring pattern; a first semiconductor chip above the first wiring structure; a second semiconductor chip above the first wiring structure and spaced apart from the first semiconductor chip in a horizontal direction; an adhesive layer including a first portion on an upper surface of the first semiconductor chip, and further including a second portion on an upper surface of the second semiconductor chip; a molding member on the first wiring structure and surrounding side surfaces of each of the first semiconductor chip, the second semiconductor chip, and the adhesive layer; and a heat dissipation member on an upper surface of each of the molding member and the adhesive layer.

The present invention provides a photonic device, comprising a photonic integrated circuit including a waveguide structure having a core layer and a cladding layer surrounding the core layer, a first cavity formed through a top surface of the photonic integrated circuit and at least partly into the cladding layer, an adhesive layer formed on at least a first surface of the first cavity, and a first photonic element arranged in the first cavity and bonded to the adhesive layer on the first surface of the first cavity, wherein at least a portion of the cladding layer and a portion of the adhesive layer define a first coupling region configured to enable coupling of an optical mode between the core layer and the first photonic element through the coupling region. Further the present invention provides a corresponding method for manufacturing a photonic device as well as.

A wiring substrate includes a first insulating layer, a first wiring layer formed on the first insulating layer, an N number of insulating layers formed on the first insulating layer and covering the first wiring layer, a cavity formed in the N number of insulating layers and exposing part of the first insulating layer, an electronic component disposed in the cavity and including an electrode covered by the first insulating layer, a filling insulating layer covering the electronic component in the cavity, first via wiring extending through the first insulating layer and connected to the electrode, and a second wiring layer formed on the first insulating layer and electrically connected by the first via wiring to the electrode. The cavity has an opening width that decreases toward the first insulating layer, and the first via wiring has a diameter that decreases toward the electronic component.

Provided is an electronic device, which includes a substrate, a via, a conductive element and a circuit structure. The via penetrates through the substrate and includes a first via and a second via. The conductive element is disposed in the via and includes a first conductive element and a second conductive element. The first conductive element is disposed in the first via. The second conductive element is disposed in the second via. The circuit structure is disposed on the substrate and is electrically connected to the conductive element. In a first direction, there is a first spacing between the two adjacent first conductive elements. There is a second spacing between the two adjacent second conductive elements. The first spacing is greater than the second spacing.

There is a method for making a substrate by providing a Si top surface in a plane, and providing a GaN top surface in the plane adjacent the Si top surface, wherein a substrate is formed having a top surface comprising the Si top surface and the GaN top surface. There is a substrate having a Si top surface in a plane, and a GaN top surface in the plane adjacent the Si top surface. There is a package having a substrate with a Si top surface in a plane, and a GaN top surface in the plane adjacent the Si top surface, a CMOS chip attached to the Si top surface, a GaN transistor attached to the GaN top surface, and a metal layer connecting the CMOS chip and the GaN transistor.

A wafer-scale system in package structure includes: a silicon substrate; a plurality of functional sub-modules arranged in an array mounted on the upper surface of the silicon substrate; a warping and stress adjustment structure mounted on the upper surface of the silicon substrate at the edges of the functional sub-modules; a stress cushioning flexible member structure mounted on the upper surface of the silicon substrate at the corner heads of the functional sub-modules; edge dummy devices of different sizes mounted on the upper surface of the edge area of the silicon substrate outside the array of the functional sub-modules; and a molding layer located on the upper surface of the silicon substrate, covering the functional sub-modules, the warping and stress adjustment structure, the stress cushioning flexible member structure and edge dummy devices.

One aspect of the present disclosure pertains to a package structure. The package structure includes a die bonded to a substrate, where a plurality of first channels are formed on a top surface of the die; a lid bonded to the substrate and over the die; and a thermal interface material (TIM) disposed between and contacting the lid and the die, where the thermal interface material fills the first channels.