A device comprises a substrate) of a first material with a surface, which is modified by depositing a bi-layer nanoparticle film. The film includes a nanoparticle layer of a second material on top of and in contact with surface, and a nanoparticle layer of a third material on top of and in contact with the nanoparticle layer of the second material. The nanoparticles of the third material adhere to the nanoparticles of the second material. The substrate region adjoining surface comprises an admixture of the second material in the first material. A fourth material contacts and chemically/mechanically bonds to the nanoparticle layer of the third material.

A semiconductor die is arranged at a mounting region of a surface of a substrate. A substrate includes electrically conductive leads around a die pad including a mounting region. A metallic layer is located at one or more portions of the substrate including the mounting region. A semiconductor die is arranged at a mounting region. The metallic layer is selectively exposed at portions less than all of the metallic layer to an oxidizing plasma to produce a patterned oxide layer including oxides of metallic material in the metallic layer. An electrically insulating encapsulation is molded onto the surface of the substrate to encapsulate the semiconductor die. The oxides of metallic material in the patterned oxide layer facilitate adhesion of the electrically insulating encapsulation to the surface of the substrate.

A packaged lateral semiconductor device includes a resistor connected between the device substrate and a package ground point. The packaged device avoids the drawbacks of a floating substrate, and reduces substrate leakage current and increases breakdown voltage relative to conventionally packaged structures. Moreover, device substrate leakage current and breakdown voltage may be controlled by selecting a value of the resistor. Exemplary devices include high voltage lateral devices such as high-electron mobility transistors (HEMTs), implemented in technologies such as GaN or GaAs, where the packaging achieves high breakdown voltage with improved dynamic behavior.

A semiconductor package carrier structure is provided and includes a substrate body, a dielectric material, and a patterned circuit layer. The substrate body has a plurality of openings, a plurality of conductive pillars, and at least one die placement portion. The dielectric material is disposed in the plurality of openings. The patterned circuit layer is disposed on a surface of the substrate body. Side surfaces of the plurality of conductive pillars and the die placement portion are all in a concave arc shape. The patterned circuit layer includes a die placement pad corresponding to the die placement portion and a plurality of bonding pads corresponding to the plurality of conductive pillars. A method of manufacturing the semiconductor package carrier structure is further provided.

A method includes removing an oxide layer from select areas of a surface of a metal structure of a lead frame to create openings that extend through the oxide layer to expose portions of the surface of the metal structure. The method further includes attaching a semiconductor die to the lead frame, performing an electrical connection process that electrically couples an exposed portion of the surface of the metal structure to a conductive feature of the semiconductor die, enclosing the semiconductor die in a package structure, and separating the electronic device from the lead frame. In one example, the openings are created by a laser ablation process. In another example, the openings are created by a chemical etch process using a mask. In another example, the openings are created by a plasma process.

A semiconductor device according to the present disclosure includes: a lead frame having a plurality of die pad portions electrically independent from each other; a power semiconductor element provided on each of the die pad portions; a wire electrically connecting the power semiconductor element and the lead frame; an epoxy-based resin provided on at least a part of the lead frame; and a sealing resin covering at least each of the die pad portions, the power semiconductor element, the wire, and the epoxy-based resin.

A bonding region is specified by having a horizontal line partially constituting crosshairs displayed on a monitor of a wire bonding apparatus superimposed on a first line segment of a first marker, and having a vertical line partially constituting the crosshairs superimposed on a first line segment of a second marker.

A pre-molded leadframe includes a laminar structure having empty spaces therein and a first thickness with a die pad having opposed first and second die pad surfaces. Insulating pre-mold material is molded onto the laminar structure. The pre-mold material penetrates the empty spaces and provides a laminar pre-molded substrate having the first thickness with the first die pad surface left exposed. The die pad has a second thickness that is less than the first thickness. One or more pillar formations are provided protruding from the second die pad surface to a height equal to a difference between the first and second thicknesses. With the laminar structure clamped between surfaces of a mold, the first die pad surface and pillar formations abut against the mold surfaces. The die pad is thus effectively clamped between the clamping surfaces countering undesired flashing of the pre-mold material over the first die pad surface.

A method of forming a package structure includes disposing a die adhesive layer on a wafer, lowering a partial connecting property of the die adhesive layer, separating a plurality of dies of the wafer and disposing each of the dies on a leadframe. A connecting property of a partial area of the die adhesive layer is lowered, and the connecting property of the partial area of the die adhesive layer is corresponding to a plurality of cutting streets of the wafer. The dies are separated according to the cutting streets of the wafer. The partial area of the die adhesive layer is corresponding to a plurality of leads of the leadframe, and a connecting strength between the die adhesive layer and each of the leads is lower than a connecting strength between the die adhesive layer and a die pad of the leadframe.

According to one embodiment, a semiconductor device includes first and second frames, a first semiconductor chip, a wire, and a resin. The second frame is arranged so as to face the first frame in a first direction, and has a stepped portion on an end portion of an upper surface. The first semiconductor chip is arranged on a bottom surface of the stepped portion. The wire electrically couples the first semiconductor chip and the first frame. The resin covers part of each of the first and second frames and seals the first semiconductor chip and the wire. A lower surface of the first frame and a side surface of the first frame in the first direction are exposed from the resin. A lower surface of the second frame and a side surface of the second frame in the first direction are exposed from the resin.