A technique includes: (a) forming a second film, whose etching rate is a second etching rate that is equal to or lower than a first etching rate of a first film when a first gas capable of removing at least a portion of the first film is supplied, on the first film; and (b) supplying the first gas to the first film.

A memory structure including a storage transistor having a data storage storage region, a gate terminal, a first drain or source terminal, and a second drain or source terminal, the storage transistor being configurable to have a threshold voltage that is representative of data stored in the data storage region; a word line electrically connected to the gate terminal, configured to provide a control voltage during a read operation; a bit line electrically connecting the first drain or source terminal to data detection circuitry; and a source line electrically connected to the second drain or source terminal, configured to provide a capacitance sufficient to sustain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during the read operation.

A method of manufacturing a display device includes forming a first amorphous silicon layer on a substrate on which a first area and a second area are defined, forming a mask in the second area on the first amorphous silicon layer, forming a preliminary second amorphous silicon layer on the first amorphous silicon layer and the mask, forming a second amorphous silicon layer by removing a portion of the preliminary second amorphous silicon layer on the mask, removing the mask, and forming a polycrystalline silicon layer by crystallizing the first amorphous silicon layer and the second amorphous silicon layer.

An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced.

A method for manufacturing a semiconductor device with high productivity is provided. The method includes a step of forming a first insulator, a second insulator, and a third insulator in this order using a multi-chamber apparatus; a step of forming a fourth insulator, a fifth insulator, a first oxide film, a second oxide film, and a third oxide film in this order using a multi-chamber apparatus; a step of forming a conductive film; a step of processing the first oxide film, the second oxide film, the third oxide film, and the conductive film, thereby forming a first oxide, a second oxide, an oxide layer, and a conductive layer each having an island shape; a step of forming a sixth insulator and an insulating film in this order using a multi-chamber apparatus; a step of planarizing the insulating film; a step of forming, in the insulating film and the sixth insulator, an opening where the second oxide is exposed; a step of forming a seventh insulator and a first conductor; and a step of forming an eighth insulator and a ninth insulator in this order using a multi-chamber apparatus.

There is a method for making a substrate by providing a Si top surface in a plane, and providing a GaN top surface in the plane adjacent the Si top surface, wherein a substrate is formed having a top surface comprising the Si top surface and the GaN top surface. There is a substrate having a Si top surface in a plane, and a GaN top surface in the plane adjacent the Si top surface. There is a package having a substrate with a Si top surface in a plane, and a GaN top surface in the plane adjacent the Si top surface, a CMOS chip attached to the Si top surface, a GaN transistor attached to the GaN top surface, and a metal layer connecting the CMOS chip and the GaN transistor.