A method and device for bonding chips onto a substrate or onto further chips. The chips are bonded onto the substrate or the further chips by means of a direct bond.

A bonding apparatus includes a first holder, a second holder, a moving unit, a housing, an interferometer, a first gas supply and a second gas supply. The first holder is configured to attract and hold a first substrate. The second holder is configured to attract and hold a second substrate. The moving unit is configured to move a first one of the first holder and the second holder in a horizontal direction with respect to a second one thereof. The interferometer is configured to radiate light to the first one or an object moved along with the first one to measure a horizontal distance thereto. The first gas supply is configured to supply a clean first gas to an inside of the housing. The second gas supply is configured to supply a second gas to a space between the interferometer and the first one or the object.

A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

Methods and apparatus of hybrid bonding with inspection are provided herein. In some embodiments, a method of hybrid bonding with inspection includes: cleaning a substrate via a first cleaning chamber and a tape frame having a plurality of chiplets via a second cleaning chamber; inspecting, via a first metrology system, the substrate for pre-bond defects in a first metrology chamber and the tape frame for pre-bond defects in a second metrology chamber; bonding one or more of the plurality of chiplets to the substrate via a hybrid bonding process in a bonder chamber to form a bonded substrate; and performing, via a second metrology system different than the first metrology system, a post-bond inspection of the bonded substrate via a third metrology chamber for post-bond defects.

Methods of hybrid bonding with inspection are provided herein. In some embodiments, a method of hybrid bonding with inspection includes: cleaning a substrate via a first cleaning chamber and a tape frame having a plurality of chiplets via a second cleaning chamber; inspecting, via a first metrology system, the substrate for pre-bond defects in a first metrology chamber and the tape frame for pre-bond defects in a second metrology chamber; bonding one or more of the plurality of chiplets to the substrate via a hybrid bonding process in a bonder chamber to form a bonded substrate; and performing, via a second metrology system different than the first metrology system, a post-bond inspection of the bonded substrate via a third metrology chamber for post-bond defects.

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

The present disclosure provides a method for manufacturing a semiconductor package. The method includes disposing a first semiconductor substrate on a temporary carrier and dicing the first semiconductor substrate to form a plurality of dies. Each of the plurality of dies has an active surface and a backside surface opposite to the active surface. The backside surface is in contact with the temporary carrier and the active surface faces downward. The method also includes transferring one of the plurality of dies from the temporary carrier to a temporary holder. The temporary holder only contacts a periphery portion of the active surface of the one of the plurality of dies.

Disclosed herein are methods for direct bonding. In some embodiments, a direct bonding method comprises preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; and after the preparing, providing a protective layer over the prepared first bonding surface of the first element, the protective layer having a thickness less than 3 microns.

A process flow for bonding a die to a substrate incorporates defectivity risk management and yield promotion by reducing flow complexity. In some embodiments, the process flow may include a radiation process on a component substrate to weaken an adhesive bonding of dies from a surface of the component substrate, a first wet clean process on the component substrate after the radiation process to clean die bonding surfaces, eject and pick processes after performing the first wet clean process to remove dies from the component substrate for bonding to a substrate, a plasma activation process on the substrate, a second wet clean process after the plasma activation process on the substrate to clean a substrate bonding surface of the substrate, and a hybrid bonding process to bond die bonding surfaces of the dies to the substrate bonding surface of the substrate.

Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.