An integrated circuit device, having a first number of terminals, and a first plurality of functional circuits including a second number of functional circuits requiring access to the terminals in the first number of terminals, where the second number is greater than the first number, includes a second plurality of functional circuits from among the first plurality of functional circuits, the second plurality of functional circuits sharing access to a shared terminal among the first number of terminals, and a respective isolation circuit between the shared terminal among the first number of terminals and each respective functional circuit in the second plurality of functional circuits, the respective isolation circuit being configured to prevent coupling of noise from one respective functional circuit in the second plurality of functional circuits to another respective functional circuit in the second plurality of functional circuits via the shared terminal.

Various aspects of the present disclosure generally relate to a bonding pad configuration. A device includes a die including multiple bonding pads, pad configuration circuitry, and control circuitry. The pad configuration circuitry is configured to, based on a routing configuration, selectively connect multiple nodes of first circuitry to a first set of bonding pads of the multiple bonding pads. The control circuitry is connected to the pad configuration circuitry and configured to obtain the routing configuration.

An integrated circuit has fuses that are selectively configurable by laser light having a wavelength incident on the fuses. A substrate of the integrated circuit has circuitry thereon. Fuses are disposed vertically above at least a portion of the circuitry. A dielectric reflector is disposed vertically above and laterally covers at least a portion of the circuitry. The dielectric reflector has a plurality of alternating dielectric layers of different refractive indices and is disposed adjacent to the fuses. The dielectric reflector is configured to reflect at least a portion of the laser light at the wavelength incident thereto.

An antifuse structure including a first metal line, a top via above and directly contacting the first metal line, a second metal line, and a conductive etch stop layer separating both the first metal line and the second metal line from an underlying layer, where a first portion of the conductive etch stop layer directly beneath the first metal line comprises a first extension region and a second portion of the conductive etch stop layer directly beneath the second metal line comprises a second extension region opposite the first extension region.

Structures for an electronic fuse and methods of forming an electronic fuse. The structure comprises an electronic fuse including a first terminal, a second terminal, and a fuse link extending from the first terminal to the second terminal. The first terminal, the second terminal, and the fuse link each include a semiconductor layer and a silicide layer. The silicide layer includes a first portion on the first terminal, a second portion on the second terminal, and a third portion on the fuse link. The fuse link includes an airgap between the semiconductor layer and the third portion of the silicide layer.

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.

A tunable coupler for making a controllable coupling to at least a first qubit is disclosed. The tunable coupler includes a first constant coupling element and a tunable coupling element. The first constant coupling element forms a non-galvanic coupling interface to at least the first qubit at a first extremity that is distant from the tunable coupling element. The tunable coupling element is located adjacent to a non-galvanic coupling interface formed as an interface to a circuit element at a second extremity thereof.

The present disclosure relates to semiconductor structures and, more particularly, to e-fuse structures and methods of manufacture. The structure includes: a silicided fuse structure which includes a narrow portion and wider, end portions; dummy structures on opposing sides of the silicided fuse structure; and sidewall spacer material separating the dummy structures from the silicided fuse structure.

Example embodiments are directed to a semiconductor package for improving Signal Integrity (SI) characteristics. The semiconductor package includes a package substrate, a mediate substrate arranged on the package substrate and including an active layer and a wiring layer, and at least two semiconductor devices on the mediate substrate. The wiring layer includes path wirings configured to connect the at least two semiconductor devices to each other. The path wirings include n paths (n is an integer that is 2 or more), and the active layer includes a selection circuit configured to select one of the n paths.