A semiconductor device is provided. The semiconductor device includes an interlayer dielectric layer; and a plurality of metal contacts formed in the interlayer dielectric layer. The plurality of metal contacts include a plurality of shallow metal contacts having a first depth, and a plurality of deep metal contacts having a second depth that is greater than the first depth, wherein a first one of the shallow metal contacts overlaps and directly contacts a first one of the deep metal contacts, and wherein the plurality of metal contacts have an equal spacing therebetween.

A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a first energy removable structure disposed in the first dielectric layer. The semiconductor device structure also includes a second dielectric layer disposed over the first dielectric layer, and an N.sup.th dielectric layer disposed over the second dielectric layer. The N is an integer greater than 2. The semiconductor device structure further includes a first conductor disposed in the N.sup.th dielectric layer, and an (N+1).sup.th dielectric layer disposed over the N.sup.th dielectric layer. A top surface of the first conductor is exposed by a first opening, and a top surface of the first energy removable structure is exposed by a second opening.

Provided is a method of manufacturing an integrated circuit device. The method includes forming a semiconductor device, wherein the semiconductor device has one or more source/drain structures, one or more channel structures and wherein the substrate is on a first side of the semiconductor device. The method also includes forming a back-end-of-line (BEOL) region and forming a bottle-neck shaped backside contact structure in the substrate and in contact with a first source/drain structure of the semiconductor device, wherein the bottle-neck shaped backside contact structure has a first side contacting the first source/drain structure, a second side contacting a backside power rail, and sidewalls extending from the first source/drain structure to the backside power rail; and wherein the backside contact structure has a first region having a positive slope and a second region, adjacent to the first region, having no slope.

Novel semiconductor devices are taught. The novel devices include a thin film transistor (TFT) with an n-type semiconductor layer to form a channel between a source and a drain. The TFT further includes a source-channel interfacial member adjacent to at least the source contact of the device to provide depletion layer control of the operation of the TFT.

A memory device includes a stacked structure having an array region and a staircase region adjacent to the array region, a lower isolation structure in the stacked structure, two memory strings in the array region and at least one lower support member in the staircase region. The stacked structure includes conductive layers. The lower isolation structure has an upper surface in a lower portion of the stacked structure, extends from the array region to the staircase region and separates one conductive layer into a first conductive strip and a second conductive strip electrically isolated from each other and electrically connected to two memory strings respectively. A material of the lower support member is the same as a material of the lower isolation structure, and a height of the lower support member is the same as a height of the lower isolation structure.

A semiconductor device includes a substrate, a first power supply line supplied with a first potential, a second power supply line supplied with a second potential, and a third power supply line supplied with a third potential, the first power supply line, the second power supply line, and the third power supply line being formed below the upper surface of the substrate, a first transistor formed above the substrate and arranged at a position overlapping the first power supply line in a plan view, a second transistor formed above the substrate, and a first via formed in the substrate and connected to a source of the first transistor and the first power supply line.

A semiconductor structure comprises two or more interconnect lines of a first width in a given interconnect level, and two or more interconnect lines of a second width in the given interconnect level. The two or more interconnect lines of the second width are disposed between a first one of the two or more interconnect lines of the first width and a second one of the two or more interconnect lines of the second width. The two or more interconnect lines of the first width have sidewalls with a negative taper angle. The two or more interconnect lines of the second width have sidewalls with a positive taper angle.

Semiconductor devices, and methods of their formation, are provided. The semiconductor device can include a substrate; a wiring level within the substrate; and at least one buried power rail within the wiring level, wherein the at least one buried power rail is divided into a plurality of rail segments, wherein each rail segment of the plurality of rail segments has a length smaller than a total length of the buried power rail.

A semiconductor structure including a first transistor including a first placeholder and a first gate pitch and a second transistor including a second placeholder and a second gate pitch, where the first gate pitch is less than the second gate pitch, and wherein the first placeholder is smaller than the second placeholder.

A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer, and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.