A standard cell layout that may be implemented in FinFET devices or nanosheet FET devices is disclosed. The standard cell layout includes power supply connections from both a topside metal layer and a backside metal layer. A device in the standard cell may be connected to both the topside metal layer and the backside metal layer. Source/drain regions of the device may be connected the metal layers using via contacts within the standard cell layout. Connections to power supply rails from the topside metal layer and the backside metal layer may also be included in the standard cell layout. The rails may be connected to a power supply such that the power supply provides power to the device through both the topside and backside metal layers.

Provided in the present application are a chip packaging structure and a preparation method therefor. The chip packaging structure comprises a substrate, a chip, an insulating layer, a capacitor structure and a packaging layer. According to the chip packaging structure and the packaging method therefor provided in the present application, a capacitor structure is packaged on a surface and a lateral wall of a chip, such that the capacitor structure is applied in packaging, thereby improving the level of integration of the chip. In the present application, a first electrode layer, a second electrode layer and a capacitive dielectric layer all extend along a surface on a side of a chip facing away from a substrate and along a lateral wall of the chip. Therefore, a larger relative area of the first electrode layer and the second electrode layer can be obtained, which can improve the capacity of a capacitor.

A vertical semiconductor device includes lower circuit patterns disposed on a first substrate. A bonding layer is disposed on the lower circuit patterns. A wire is disposed on the bonding layer. A cell stack structure is disposed on the wire. A base pattern is disposed on the cell stack structure. An upper insulating layer is disposed on the base pattern. A cell contact plug passes through the cell stack structure and extends to the upper insulating layer. A through-plug is disposed inside a through-hole formed through an outer side of the base pattern to extend to the upper insulating layer. Each of the cell contact plug and the through-plug includes a barrier metal pattern and a metal pattern, and the barrier metal pattern is disposed along sidewalls and bottom surfaces of the cell contact hole and the through-hole.

A semiconductor device may include a gate structure, first and second source/drain layers, first and second contact plugs, first and second conductive structures, and a third contact plug. The gate structure may be on a substrate. The first and second source/drain layers may be at upper portions, respectively, of the substrate on opposite sidewalls of the gate structure and adjacent thereto. The first and second contact plugs may be on the first and second source/drain layers, respectively, and each contact plugs may extend in a vertical direction. The first and second conductive structures may contact upper surfaces of the first and second contact plugs, respectively. The third contact plug may contact an upper surface of the second conductive structure. A height and a width of the second conductive structure may be greater than a height and a width of the first conductive structure.

A semiconductor structure includes a semiconductor fin protruding from a substrate; a gate structure engaging with the semiconductor fin. The semiconductor structure also includes an interlayer dielectric (ILD) layer disposed over the substrate and adjacent to the gate structure, where a top surface of the gate structure is below a top surface of the ILD layer; a first metal layer in direct contact with a top surface of the gate structure; a second metal layer disposed over the first metal layer, where the first metal layer is disposed on bottom and sidewall surfaces of the second metal layer, where the bottom surface of the second metal layer has a concave profile, and where the second metal layer differs from the first metal layer in composition; and a gate contact disposed over the second metal layer.

A memory die includes first and second memory-region alternating stacks of memory-region insulating layers and electrically conductive layers that are laterally spaced apart from each other by a respective first portion of a retro-stepped dielectric structure overlying first stepped surfaces of the first and second memory-region alternating stacks, memory opening fill structures located the first and second memory-region alternating stacks, and a peripheral alternating stack of peripheral insulating layers and spacer material which is laterally spaced from the second memory-region alternating stack by a second portion of the retro-stepped dielectric structure overlying second stepped surfaces of the second memory-region alternating stack. Bottom surfaces of the first and second memory-region alternating stacks are spaced apart by a first lateral spacing distance, and bottom surfaces of the second memory alternating stack and the peripheral alternating stack are spaced apart by the first lateral spacing distance.

A die including a die body having a first body surface, a second body surface on an opposite side of the die body as the first body surface, an interconnect region adjacent to the first body surface including interconnect dielectric layers with metal lines and vias, a transistor region above the interconnect region, the metal lines and vias making electrical connections to one or more power rails of the transistor region and electrically connected to transistors of the transistor region, a power region above the transistor region including an electro-conductive film on the second body surface and TSVs in the power region, an outer end of the TSV contacting the film and an embedded end of the TSVs contacting one of the power rails. A method of manufacturing an IC package and computer with the IC package are also disclosed.

Methods, devices, and systems for driving optical modulators. An example integrated circuit includes a driver including: a first circuit having a first switch coupled between a first input and a first output and a second circuit having a second switch coupled between a second input and a second output. Each of the first and second switches is configured to receive a control signal adjustable to control a corresponding signal path with a corresponding input electronic signal. The first and second circuits are configured to control a rising edge and a falling edge of an output electronic signal at an output of the driver that is based on a first output electronic signal at the first output and a second output electronic signal at the second output. The output of the driver is electrically coupled to the optical modulator to provide the output electronic signal to modulate an optical signal.

A semiconductor device and a logic device formed of the semiconductor device are provided. The semiconductor device includes a first field effect transistor (FET), disposed on a semiconductor substrate, and including vertically separated first channel structures formed as thin sheets each having opposite major planar surfaces facing toward and away from the semiconductor substrate; and a second FET, disposed on the semiconductor substrate and overlapped with the first FET. A conductive type of the second FET is complementary to a conductive type of the first FET. Second channel structures of the second FET are separately arranged along a lateral direction, and formed as thin walls.

A package structure is provided. The package structure includes a first interconnect structure over a first substrate. The package structure also includes a second interconnect structure below a second substrate. The package structure further includes a bonding structure between the first interconnect structure and the second interconnect structure. The bonding structure comprises a first intermetallic compound (IMC) and a second intermetallic compound (IMC). In addition, the package structure includes a first seed layer below the bonding structure. The package structure also includes a second seed layer over the second IMC. Opposite sidewalls of the second seed layer are covered by the second IMC.