In a general aspect, a power module includes a substrate having first, second and third patterned metal layers disposed on a surface of the substrate. The module also includes a first high-side transistor disposed on the first patterned metal layer, a second high-side transistor disposed on the first patterned metal layer, a first conductive clip electrically coupling the first high-side transistor with the second patterned metal layer, and a second conductive clip electrically coupling the second high-side transistor with the second patterned metal layer. The module further includes a first low-side transistor disposed on the second patterned metal layer, a second low-side transistor disposed on the second patterned metal layer, a third conductive clip electrically coupling the first low-side transistor with the third patterned metal layer, and a fourth conductive clip electrically coupling the second low-side transistor with the third patterned metal layer.

A semiconductor device, including: a semiconductor chip including an electrode on an upper surface thereof; and a wiring member including a bonding portion, a rising portion, and a connecting portion, the bonding portion being bonded to the electrode via a bonding material, the rising portion being of a shape of a flat plate and extending upward from the bonding portion, the connecting portion connecting the bonding portion to the rising portion. The rising portion includes a lower region connected to the connecting portion and an upper region located above the lower region. Both the lower region and the connecting portion have a first thickness, and the upper region has a second thickness that is larger than the first thickness.

A semiconductor assembly includes a top substrate and a base substrate attached to top and bottom electrode layers of a semiconductor device, respectively. The top substrate includes an electrode connection plate thermally conductible with and electrically connected to the top electrode layer of the semiconductor device and vertical posts protruding from the electrode connection plate and electrically connected to the base substrate. The base substrate includes an electrode connection slug embedded in a dielectric layer and thermally conductible with and electrically connected to the bottom electrode layer of the semiconductor device and first and second routing circuitries deposited on two opposite surfaces of the dielectric layer, respectively, and electrically connected to each other.

According to one embodiment, a semiconductor apparatus includes: a wiring board having a first through-hole; a first substrate including a first conductive layer, a first insulating layer on the first conductive layer, and a second conductive layer on the first insulating layer, the first substrate being provided in the first through-hole; a first semiconductor chip provided on the first substrate in the first through-hole; and a sealing member that covers the first substrate and the first semiconductor chip in the first through-hole, wherein a first dimension of the first insulating layer in a first direction parallel to a surface of the first substrate is larger than a second dimension of the first conductive layer in the first direction and a third dimension of the second conductive layer in the first direction.

A connector for contacting a semiconductor chip. The connector may include a tab, where the tab includes an outer portion, having a planar shape, the outer portion having a lower surface, adapted to contact a surface of the semiconductor chip, and an upper surface that defines a main plane of the tab. The tab may also include a ring portion, the ring portion connected to the outer portion and extending proud of the main plane, wherein the ring portion defines an inner hole within the tab structure, the inner hole being adapted to expose a contact portion of the surface of the semiconductor chip, wherein the ring portion includes at least two slots. The connector may further include a clip, comprising a connection portion, the connection portion having an aperture that is adapted to couple around the ring portion.

A joint structure includes a first conductor and a second conductor, and a laminated bonding material that is arranged between the first conductor and the second conductor to bond the first conductor to the second conductor. The laminated bonding material includes a first bonding material layer bonded to the first conductor, a second bonding material layer bonded to the second conductor, and an auxiliary conductor plate arranged between the first bonding material layer and the second bonding material layer. The auxiliary conductor plate has a melting point higher than melting points of the first bonding material layer and the second bonding material layer. The second conductor has a laser irradiation mark on a back surface thereof, the back surface being opposite to a front surface of the second conductor that faces the laminated bonding material.

A semiconductor device includes a first conductive portion, a second conductive portion, a first semiconductor element, a second semiconductor element, two first terminals, a second terminal, a third terminal, a first conductive member, a second conductive member, a plurality of first control terminals, a plurality of second control terminals, and a sealing resin. In a first direction orthogonal to the thickness direction, the first conductive portion and the second conductive portion are spaced apart from each other. The second terminal and the second conductive member form a conduction path located outside the plurality of first control terminals in a second direction orthogonal to the thickness direction and the first direction.

A metal clip disposed on chips to connect the chips to each other, includes a plurality of bonding parts each having a lower surface configured to bond to an upper surface of each of the chips; and an outer side part formed at each of the bonding parts to extend upward from at least a portion of an outer side of respective ones of the bonding parts to form a step therefrom.

A method of manufacturing a device package. The method comprises patterning a first substrate to form patterned regions comprising a thermal oxide layer. The method further comprises directly bonding the patterned regions of the first substrate to a second substrate to form a bonding interface. The bonded first and second substrates form an integrated cooling assembly comprising a coolant chamber volume. Portions of the first substrate exposed to the coolant chamber volume comprise a native oxide layer.

Various aspects relate to mechanisms for coupling a three-dimensional semiconductor cube to a host substrate including a plurality of substrate communication points. The three-dimensional semiconductor cube includes a plurality of cube communication points corresponding to the plurality of substrate communication points and at least one mounting mechanism that couples the three-dimensional semiconductor cube to the host substrate.