A semiconductor package includes a lead frame, a low side field-effect transistor (FET), a high side FET, a metal clip, and a molding encapsulation. The low side FET is flipped and is attached to a first die paddle of the lead frame. The lead frame comprises one or more voltage input (Vin) leads; a gate lead; one or more switching node (Lx) leads; a first die paddle; a second die paddle; and an end paddle. Each of an exposed bottom surface of the one or more Lx leads is directly connected to an exposed bottom surface of the end paddle. A longitudinal direction of an exposed bottom surface of the gate lead is perpendicular to a longitudinal direction of each of the exposed bottom surface of the one or more Lx leads. An entirely of each of the one or more Vin leads is of the full thickness.

A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

A discrete semiconductor package includes a semiconductor device, a left lead, and a right lead. The semiconductor device has a first side and a second side, the second side being opposite the first side. The left lead has a left terminal and a platform to support the semiconductor device on the first side. The right lead has a right terminal and a clip coin to support the semiconductor device on the second side.

A lead frame includes a support portion that has one end on which a first part and a second part that has a smaller thickness than the first part are arranged, a lead, and a heat sink that is welded to the support portion in the second part. A method of manufacturing the lead frame includes forming, from a metal plate, a frame member that includes a support portion and a lead, where the support portion has one end on which a first part and a second part that has a smaller thickness than the first part are arranged, and welding a heat sink to the support portion in the second part.

A semiconductor device includes a laminate including a semiconductor element, an insulating substrate on a first surface of the semiconductor element, an interconnect on the insulating substrate, and an interconnect member on a second surface of the semiconductor element. The interconnect is electrically connected to a first electrode in the first surface of the semiconductor element through a through hole in the insulating substrate. The interconnect member is electrically connected to a second electrode in the second surface of the semiconductor element. The semiconductor device further includes first and second elastic terminals holding the laminate therebetween. The first terminal includes a bulge that engages with a depression in the interconnect. The second terminal contacts the interconnect member. The semiconductor device further includes a fixing member fixing the first terminal and the second terminal while electrically isolating the first terminal and the second terminal from each other.

A semiconductor device includes a semiconductor chip having a first chip surface and a second chip surface, and a connector member having a bonding portion that faces the first chip surface and a connection portion. The connection portion is connected to an end portion of the bonding portion on one side in a second direction, and located on the other side in a first direction toward one side in the second direction. The bonding portion has a first bonding surface bonded to the first chip surface. A first recessed portion that is recessed on one side in the first direction and is open to the other side in the second direction is provided in the first bonding surface. A dimension of the first recessed portion in the second direction is 40% or more and 60% or less of a dimension of the bonding portion in the second direction.

A transistor package includes a transistor chip having opposing first and second main sides, and a first load electrode and a second load electrode on the first main side, with a carrier facing the second main side. A first terminal post is arranged laterally beside the transistor chip. A second terminal post is arranged laterally beside the transistor chip on an opposite side. A first clip connects the first load electrode to the first terminal post. A second clip connects the second load electrode to the second terminal post. At least one of the clips includes a first contact element which projects from a first side wall of the clip and is bent downwards in a direction towards the transistor chip to electrically contact the first or second load electrode of the chip, a bending axis being in a longitudinal direction of the clip.

A semiconductor package includes a transistor chip having first and second opposite facing sides. The semiconductor transistor chip includes a first load electrode and a second load electrode on the first side. The package includes a carrier facing the second side of the chip, a first terminal post laterally beside the transistor chip and a second terminal post laterally beside the transistor chip. The second terminal post is a part of the carrier or physically connects to the carrier. A first clip connects the first load electrode to the first terminal post. A second clip connects the second load electrode to the second terminal post. An upper surface of the first terminal post and an upper surface of the second terminal post are arranged at different levels of height. The first clip and the second clip are of same shape.

An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

A semiconductor structure is provided. The semiconductor structure includes a lead frame and a sub-substrate disposed on the lead frame, wherein the thickness of the sub-substrate is between 0 and 0.5 m. The semiconductor structure also includes an epitaxial layer disposed on the sub-substrate. The epitaxial layer includes a buffer layer, a channel layer and a barrier layer. The buffer layer is disposed between the sub-substrate and the channel layer. The channel layer is disposed between the buffer layer and the barrier layer. The semiconductor structure further includes a device layer disposed on the barrier layer and an interconnector structure electrically connected to the epitaxial layer and/or the device layer by a through hole.