A semiconductor structure is provided. The semiconductor structure includes a lead frame and a sub-substrate disposed on the lead frame, wherein the thickness of the sub-substrate is between 0 and 0.5 m. The semiconductor structure also includes an epitaxial layer disposed on the sub-substrate. The epitaxial layer includes a buffer layer, a channel layer and a barrier layer. The buffer layer is disposed between the sub-substrate and the channel layer. The channel layer is disposed between the buffer layer and the barrier layer. The semiconductor structure further includes a device layer disposed on the barrier layer and an interconnector structure electrically connected to the epitaxial layer and/or the device layer by a through hole.

Die attach materials are provided. In one example, the die-attach material includes a plurality of core-shell particles. Each core-shell particle includes a core and a shell on the core. The core includes a conducting material. The shell includes a metal nitride.

An electronic device which can suppress peeling off and damaging of the bonding material is provided. The electronic device includes an electronic component, a mounting portion, and a bonding material. The electronic component has an element front surface and an element back surface separated in the z-direction. The mounting portion has a mounting surface opposed to the element back surface on which the electronic component is mounted. The bonding material bonds the electronic component to the mounting portion. The bonding material includes a base portion and a fillet portion. The base portion is held between the electronic component and the mounting portion in the z-direction. The fillet portion is connected to the base portion and is formed outside the electronic component when seen in the z-direction. The electronic component includes two element lateral surface and ridges. The ridges are intersections of the two element lateral surface and extend in the z-direction. The fillet portion includes a ridge cover portion which covers at least a part of the ridges.

According to one embodiment, there is provided a semiconductor device including a chip, and a gate electrode connected to a gate electrode pad provided on the chip. The gate electrode includes an external exposed portion having an external exposed surface that is flush with an external exposed surface of a sealing resin, and a gate electrode pad connection portion continuous with the external exposed portion and connected to the gate electrode pad, the gate electrode pad connection portion including a portion sandwiched between the gate electrode pad and a part of the sealing resin.

A pixel-driving circuit for driving a digital display device, the pixel-driving circuit formed on an interposer that is electrically connected to a display substrate through a plurality of bumps. The pixel-driving circuit comprises a row terminal connected to a row bump connected to a row line of a row-driving circuit among the plurality of bumps, a column terminal connected to a column bump connected to a column line of a column-driving circuit among the plurality of bumps, a common element that shares at least one of the row terminal or the column terminal for L (L is a positive integer greater than or equal to 2) display pixels formed on the interposer, and L pixel individual elements connected to the common element and driving a plurality of light emitters included in each of the L display pixels.

Provided is a stacked ceramic capacitor package, for an electronic device, preventing noise, vibration and cracks due to piezoelectric properties. The ceramic capacitor package for an electronic device comprises: stacked ceramic capacitors; a first terminal structure connected to a first side surface of the stacked ceramic capacitors; and a second terminal structure connected to a second side surface of the stacked ceramic capacitors and disposed so as to face the first terminal structure with the stacked ceramic capacitors therebetween. The first terminal structure has a first groove defined in an area coming into contact with the first side surface of the stacked ceramic capacitors. The horizontal length of the first groove is 30% to 50% of the horizontal length of the stacked ceramic capacitors.

Provided is a stacked ceramic capacitor package, for an electronic device, preventing noise, vibration and cracks due to piezoelectric properties. The ceramic capacitor package for an electronic device comprises: stacked ceramic capacitors; a first terminal structure connected to a first side surface of the stacked ceramic capacitors; and a second terminal structure connected to a second side surface of the stacked ceramic capacitors and disposed so as to face the first terminal structure with the stacked ceramic capacitors therebetween. The first terminal structure has a first groove defined in an area coming into contact with the first side surface of the stacked ceramic capacitors. The horizontal length of the first groove is 30% to 50% of the horizontal length of the stacked ceramic capacitors.

A semiconductor device includes a first die pad, a first semiconductor element, a first lead, a first conductive member, and a sealing resin. The first conductive member is conductively bonded to the first semiconductor element and the first lead. The first die pad, the first semiconductor element, and the first conductive member are covered with the sealing resin. The first lead protrudes from the first side surface of the sealing resin. The first distance D1, the second distance D2, and the third distance D3 satisfy the relationship D1>D2D3. In the first direction z, the first conductive member is located between the first mounting surface of the first die pad and the top surface of the sealing resin.

A power electronics module, having a continuous DBC PCB having power semiconductors arranged on connecting regions of an uppermost layer of said DBC PCB and a lead frame arranged above the power semiconductors for three-dimensional power and control routing, wherein the lead frame has a drain-source connection, which can be brought into electrical contact with a drain-source contact of the PCB, and a load-source connection which is opposite the drain-source connection via the power semiconductors and which is formed from a plurality of subregions, each of which can be brought into electrical contact with one of the power semiconductors, and at least one gate-source terminal and at least one kelvin-source terminal, and a carrier element including an electrically insulating material on which conductor tracks are provided, wherein the carrier element is routed between the power semiconductors in a region between the load-source connection and the drain-source connection.

An electronic device includes: a substrate with obverse and reverse surfaces spaced apart in a thickness direction; an electronic element having an obverse surface formed with a first obverse surface electrode; a wiring portion on the substrate obverse surface and configured to transmit a control signal for the electronic element; a conduction member with obverse and reverse surfaces spaced apart in the thickness direction, where the reverse surface is joined to the wiring portion; a conductive first lead on the substrate obverse surface; and a first connecting member joined to the obverse surface of the conduction member and the first obverse surface electrode. The first lead includes a first pad portion spaced apart from the wiring portion and to which the electronic element is joined. The wiring portion and the first obverse surface electrode are electrically connected to each other via the conduction member and the first connecting member.