A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.

A wet etching chemistry to selectively remove a polymer residue on an opening embedded in a low-k dielectric layer and an underlying stop layer in a process of forming an interconnect structure is provided. The wet etching chemistry includes: two type of organic solvents, wherein a concentration of the two type of organic solvents is greater than or equal to 70%; an Alkali source amine, at least comprising a tertiary amine; an inhibitor; and water. In some embodiment, the wet etching chemistry is free of a peroxide to avoid damage to the WdC hard mask.

A method for manufacturing raised strip-shaped active areas is disclosed, including: step 1: performing etching on a semiconductor substrate to form patterning raised strip-shaped structures and shallow trenches; step 2: forming a second dielectric layer which fills the shallow trenches and extends to a surface of the first hard mask layer on top surfaces of the raised strip-shaped structures; step 3: performing the first CMP on second dielectric layer, the first CMP stops at a surface of a first hard mask layer; step 4: performing planarization adjustment on a top surface of the second dielectric layer through second wet etching to reduce a height difference of the top surface of the second dielectric layer in different areas; step 5: removing the first hard mask layer; and step 6: performing third dry etching to reduce the top surface of the second dielectric layer to below the top surface of each raised strip-shaped structure.

A method is described for method for patterning a metal layer interfaced with a transparent conductive film, in which the method comprises contacting a structure through a patterned mask with an etching solution comprising Fe.sup.+3 ions, wherein the structure comprises the metal layer comprising copper, nickel, aluminum or alloys thereof covering at least partially a transparent conductive film with conductive elements comprising silver, to expose a portion of the transparent conductive film. Etching solutions and the etched structures are also described.

A method for manufacturing a semiconductor structure includes forming a plurality of semiconductor stack portions spaced apart from each other by a plurality of recesses, each of which includes two sacrificial layer portions and a channel layer portion disposed therebetween, in which the channel layer portion has a plurality of crystal planes and is formed with a first straight lateral surface which is aligned with one of the crystal planes that has a lowest etching rate for an etchant to be used for laterally etching the channel layer portion among those of the crystal planes of the channel layer portion which are able to expose to the recesses; and laterally etching the channel layer portion using the etchant to permit the channel layer portion to be formed with a second straight lateral surface.

A substrate processing method includes a first oxidation step of heating a substrate at a first temperature by irradiation of light of a first intensity while supplying an oxygen gas or an ozone gas to the substrate, a first etching step of supplying an etching liquid to the substrate to make a surface layer of a molybdenum film that changed to molybdenum trioxide dissolve in the etching liquid, a second oxidation step of heating the substrate at a second temperature by irradiation of light of a second intensity while supplying the oxygen gas or the ozone gas to the substrate, and a second etching step of supplying the etching liquid to the substrate to make the surface layer of the molybdenum film that changed to the molybdenum trioxide dissolve in the etching liquid.

An etching method includes: (a) providing a substrate including an etching target film and a mask on the etching target film; (b) after (a), forming a metal-containing deposit on the mask by a first plasma generated from a first processing gas including a metal-containing gas and a hydrogen-containing gas; (c) after (b), deforming or modifying the metal-containing deposit by a second plasma generated from a second processing gas different from the first processing gas; and (d) after (c), etching the etching target film.

The present application provides a method of fabricating a conductive feature. The method of fabricating the conductive feature includes steps of depositing an insulative layer on a substrate, forming a trench in the insulative layer, performing a cyclic process comprising a sequence of a deposition step and a removal step to deposit a conductive material in the trench until the deposition step has been performed is equal to a first preset number of times and a number of the times the removal step has been performed is equal to a second preset number of times, and filling the trench with the conductive material after the cyclic process.

The present disclosure discloses a semiconductor device and a fabrication method thereof. In the method, firstly etching a substrate in a first device region to form at least one first trench and then etching the substrate in both first device region and second device region to form at least one first isolation trench at the positions corresponding to the at least one first trench and form at least one second isolation trench in the second device region. Herein a depth of the first isolation trench is larger than that of the second isolation trench.

Provided is an etching solution composition that can have both a higher etch selectivity of silicon nitride and a reduction in the deposition of silica on the surface of silicon oxide. An inorganic acid-based etching solution composition for selectively etching away silicon nitride from a semiconductor containing silicon nitride and silicon oxide, the etching solution composition comprising: (a) an etch inhibitor that reduces etching of silicon oxide; and (b) a deposition inhibitor that reduces deposition of silica on a surface of silicon oxide.