A semiconductor apparatus includes a substrate, a semiconductor device arranged on an upper surface of the substrate, a lead frame bonded to an upper surface of the semiconductor device via a bonding material, the lead frame having a first recess on an upper surface thereof, a wire connected to the first recess, and a resin that seals the substrate, the semiconductor device, the lead frame, and the wire.

Workability in a manufacturing process of a semiconductor device is improved. A terminal member is the terminal member joined to an electrode of a semiconductor element, and includes a conductor portion, a first annular projecting portion, and an annular recess. The conductor portion has a first main surface and a second main surface located on a side opposite to the first main surface. The first annular projecting portion is provided on the first main surface of the conductor portion. The annular recess is provided on the second main surface and is disposed at a position overlapping with the first annular projecting portion. By pressing a joining member against the first main surface of the terminal member, the first annular projecting portion can be embedded in the joining member.

Semiconductor module including a semiconductor and including a shaped metal body that is electrically contacted by the semiconductor, for forming a contact surface for an electrical conductor, wherein the shaped metal body is bent or folded. A method is also described for establishing electrical contacting of an electrical conductor on a semiconductor, said method including the steps of: fastening a bent or folded shaped metal body of a constant thickness to the semiconductor by means of a first fastening method and then fastening the electrical conductor to the shaped metal body by means of a second fastening method.

A semiconductor device includes a semiconductor chip having a first chip surface and a second chip surface, and a connector member having a bonding portion that faces the first chip surface and a connection portion. The connection portion is connected to an end portion of the bonding portion on one side in a second direction, and located on the other side in a first direction toward one side in the second direction. The bonding portion has a first bonding surface bonded to the first chip surface. A first recessed portion that is recessed on one side in the first direction and is open to the other side in the second direction is provided in the first bonding surface. A dimension of the first recessed portion in the second direction is 40% or more and 60% or less of a dimension of the bonding portion in the second direction.

A transistor package includes a transistor chip having opposing first and second main sides, and a first load electrode and a second load electrode on the first main side, with a carrier facing the second main side. A first terminal post is arranged laterally beside the transistor chip. A second terminal post is arranged laterally beside the transistor chip on an opposite side. A first clip connects the first load electrode to the first terminal post. A second clip connects the second load electrode to the second terminal post. At least one of the clips includes a first contact element which projects from a first side wall of the clip and is bent downwards in a direction towards the transistor chip to electrically contact the first or second load electrode of the chip, a bending axis being in a longitudinal direction of the clip.

According to one embodiment, a semiconductor device includes the following structure. A semiconductor chip is provided between first and second conductors. A first connector is provided between the semiconductor chip and the second conductor. The second conductor includes a first plate, a second plate, and a third plate, which are continuously provided. The first plate extends in a first direction along a main surface of the semiconductor chip and is connected to the semiconductor chip via the first connector. The second plate extends from the first plate in a direction intersecting the first direction, and includes a first surface continuous from a surface on which the first connector is provided, and includes a groove provided on the first surface. The third plate extends from the second plate in the first direction.

A power package includes at least one power substrate having at least one power trace, at least one power device on the at least one power trace, signal terminals, and at least one signal connection assembly. The at least one signal connection assembly includes at least one of the following: at least one signal trace that is thinner than the at least one power trace; at least one embedded routing layer within the at least one power substrate; and/or at least one routing layer on the at least one power substrate.

A semiconductor die package includes a semiconductor transistor die having a contact pad on an upper main face. The semiconductor die package also includes an electrical conductor disposed on the contact pad and fabricated by laser-assisted structuring of a metallic material, and an encapsulant covering the semiconductor die and at least a portion of the electrical conductor.

A metal clip disposed on chips to connect the chips to each other, includes a plurality of bonding parts each having a lower surface configured to bond to an upper surface of each of the chips; and an outer side part formed at each of the bonding parts to extend upward from at least a portion of an outer side of respective ones of the bonding parts to form a step therefrom.

A semiconductor device includes: a leadframe having a die pad, first leads and second leads, the second leads being connected with a leadpost; a first lateral transistor die having a first pad, second pad and third pad; a first clip, configured to connect the first pad to the die pad, which is connected with the first leads; and a second clip, configured to connect the second pad to the leadpost of the second leads), the leadpost being disconnected from the die pad. The second clip includes a first section contacting the second pad of the first lateral transistor die, a second section contacting the leadpost of the second leads, and a middle section between the first and the second sections. The middle section has partly a smaller width than the second section.