A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

A semiconductor device according to some embodiments includes a semiconductor die, and a bond pad on a first side of the semiconductor die for receiving a wire bond. The bond pad includes a discontinuous uppermost surface opposite the first side of the semiconductor die.

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

A method includes forming a seed layer on a substrate. The seed layer includes a first metal. The method also includes forming a first metal layer over the seed layer. The first metal layer includes a second metal. The method further includes forming a second metal layer over the first metal layer. The second metal layer includes the first metal. The method includes converting at least a portion of the first metal layer into an alloy of the first metal and the second metal. The seed layer is then etched.

One example includes a method for fabricating an integrated circuit (IC) device. The method includes fabricating a semiconductor die comprising a metal top (METTOP) structure and forming a barrier layer over the METTOP structure to cover approximately the entirety of the METTOP structure. The method also includes forming a polyimide (PI) layer over the semiconductor die and over a portion of the barrier layer to form a gap that exposes the barrier layer through the PI layer. The method further includes forming a conductive post in the gap over the barrier layer.

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

An element, a bonded structure including the element, and a method of forming the same are disclosed. The bonded structure can include a first element having a first nonconductive field region and a first conductive feature at least partially defining a bonding surface of the first element. The first conductive feature includes a first portion and a second portion over the first portion with a continuous sidewall. The second portion includes different metal composition from the first portion or comprising fluorine at the surface of the first conductive feature. A second element has a second nonconductive field region and a second conductive feature which are directly bonded to the first nonconductive field region and a first conductive feature, respectively.

An electronic component is disclosed. In one example, the electronic component comprises a semiconductor body, an active region in the semiconductor body, at least one metallization structure arranged on or above the active region and comprising a stack. The stack includes a barrier structure, an intermediate structure on the barrier structure and comprising nickel, and a copper and/or aluminium structure on the intermediate structure and comprising copper and/or aluminium. A dielectric structure is connected to a sidewall of the stack.

A described example includes: a semiconductor die having a device side surface and an opposing backside surface, the backside surface mounted to a die pad of a lead frame, the lead frame comprising conductive leads spaced from the die pad; a conductor layer overlying the device side surface; bond pads including bond pad conductors formed in the conductor layer, a nickel layer over the bond pad conductors, and a palladium or gold layer over the nickel layer; conductor traces formed in the conductor layer, the conductor traces free from the nickel layer and the palladium or gold layer; bond wires bonded to the bond pads electrically coupling the bond pads to conductive leads; and mold compound covering the semiconductor die, the bond pads, the bond wires, and portions of the lead frame, wherein portions of the conductive leads are exposed from the mold compound to form terminals.

An image pickup unit includes: an image pickup substrate including a first principal surface and a second principal surface, a light receiving circuit being formed on the first principal surface and a through wiring being placed on an inner surface of a via hole including an opening in the second principal surface; a solder resist film placed around the via hole on the second principal surface and in the via hole in a range from a bottom face to a level not reaching the second principal surface; and a bonding terminal which is made of solder, covers a surface of the solder resist film placed in the via hole, and is bonded to the through wiring on an outer edge of the opening in the via hole, the through wiring being not covered with the solder resist film.