Implementations of a semiconductor package may include one or more leads operatively coupled with one or more semiconductor devices; and a mold compound coupled to the one or more leads and exposing a flank of the one or more leads through a surface of the mold compound that may be oriented substantially perpendicularly to a longest length of the one or more leads. An exposed surface of the flank may be recessed into the surface of the mold compound. The exposed surface of the flank may include at least one curve.

A method of fabricating an electronic device includes forming an embedded die frame having a cavity and a routing structure, a semiconductor die in the cavity with a gallium nitride layer on the routing structure, and a heat spreader having a thermally conductive insulator layer and a metal plate, the thermally conductive insulator layer having a first side that faces the embedded die frame and an opposite second side that faces away from the embedded die frame, with a portion of the first side of the thermally conductive insulator layer extending over a side of a silicon substrate of the semiconductor die, and the metal plate on the second side of the thermally conductive insulator layer.

Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.

A package structure that includes a pair of substrates arranged to oppose each other so as to form an internal space; a bonding portion sealing the pair of substrates; an element is sealed in the internal space and surrounded by the pair of substrates; an adsorption layer within the internal space and opposing at least one substrate of the pair of substrates, the adsorption layer constructed to adsorbs at least hydrogen; and a diffusion-inhibiting layer between the at least one substrate and the adsorption layer, and in which hydrogen is more difficult to diffuse compared with in the at least one substrate.

A method of cooling a semiconductor package module is provided. The method includes operating a semiconductor package module immersed in a liquid coolant in a tank. The method includes applying a driving voltage to a piezoelectric element or ultrasonic vibrating element disposed on the semiconductor package module to generate a vibration. The method further includes repelling bubbles of the liquid coolant formed on a surface of the semiconductor package module by way of the vibration.

A hollow package includes a device substrate; a lid substrate provided above the device substrate; a first sealing ring provided on an upper surface of the device substrate; a second sealing ring provided on a lower surface of the lid substrate so as to face the first sealing ring; a seal layer that bonds the first sealing ring and the second sealing ring; and a functional element provided in a hollow portion surrounded by the device substrate, the lid substrate, the first sealing ring, the second sealing ring, and the seal layer, wherein the first sealing ring or the second sealing ring has a corner portion in a planar view, and the first sealing ring or the second sealing ring has a recess, which is recessed in a direction perpendicular to the upper surface of the device substrate, locally formed in a portion including the corner portion.

A spring for use in a semiconductor device is provided, which includes a body having a plurality of slits to allow the body to deflect along a first direction; and one or more legs at one or both ends of the body. The plurality of slits are located in a plurality of planes perpendicular to the first direction and distributed along the first direction. The slits in a particular plane of the plurality of planes are interleaved with the slits in an adjacent plane of the plurality of planes

Semiconductor systems having anti-warpage frames (and associated systems, devices, and methods) are described herein. In one embodiment, a semiconductor system includes (a) a printed circuit board (PCB) having a first side and a second side opposite the first side, and (b) at least one memory device attached to the PCB at the first side of the PCB. The semiconductor system further includes a frame structure attached to the PCB at the first side of the PCB and proximate the at least one memory device. The frame structure can be configured to resist warpage of the PCB, for example, when the semiconductor system is heated to attach the at least one memory device to the PCB.

The present disclosure provides a semiconductor package. The semiconductor package includes a substrate, a die, a thermally conductive material, a plurality of bonding wires, a molding compound, and a heat-dissipating frame. The substrate has opposing top and bottom surfaces. The thermally conductive material is disposed between the die and the substrate to bond the die to the top surface of the substrate. One end of each of the bonding wires is connected to the die and the other end of each of the bonding wires is connected to the top surface of the substrate. The molding compound is formed on the top surface of the substrate to cover the die and the bonding wires. The heat-dissipating frame is disposed on the top surface of the substrate to enclose the molding compound. The present disclosure further provides a method of manufacturing the above semiconductor package.

The present disclosure relates to a power semiconductor module including: a carrier; a plurality of semiconductor dies mounted onto the carrier; a housing including a frame enclosing the carrier circumferentially; a first external connection electrically connected to a first subset of the semiconductor dies, the first external connection protruding laterally from the housing at a first level; and an insert including an electrically isolating material and a second external connection mounted onto the electrically isolating material. The insert is at least partially mounted to the frame and at least partially covers the carrier and/or the first subset of the plurality of semiconductor dies. The second external connection is connected to a second subset of the plurality of semiconductor dies. The second external connection protrudes from the housing.