Patent classifications
H10P14/3402
SEMICONDUCTOR STRUCTURE
A semiconductor device includes a substrate, and a first transistor disposed on the substrate. The first transistor includes a first channel layer, a magnesium oxide layer, a first gate electrode, a first gate dielectric and first source/drain electrodes. A crystal orientation of the first channel layer is <100> or <110>. The magnesium oxide layer is located below the first channel layer and in contact with the first channel layer. The first gate electrode is located over the first channel layer. The first gate dielectric is located in between the first channel layer and the first gate electrode. The first source/drain electrodes are disposed on the first channel layer.
METHODS FOR FORMING SPACERS AND RELATED STRUCTURES
Methods for patterning and forming structures, as well as related structures and systems are disclosed. The methods comprise forming a liner on sidewalls of a patterned resist. The patterned resist comprises a first metal, and the liner comprises a second metal.
Vapor deposition of tellurium nanomesh electronics on arbitrary surfaces at low temperature
A method of fabricating semiconducting tellurium (Te) nanomesh. The method includes the steps of preparing a substrate, vaporizing Te powders under a first temperature; and growing Te nanomesh on the substrate using the vaporized Te powders under a second temperature. The first temperature is higher than the second temperature. The rationally designed nanomesh exhibits exciting properties, such as micrometer-level patterning capacity, excellent field-effect hole mobility, fast photoresponse in the optical communication region, and controllable electronic structure of the mixed-dimensional heterojunctions.
Masking layer with post treatment
A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.