A memory device comprising a memory cell over a first transistor including silicon in a semiconductor layer is provided. The memory cell includes a capacitor and a second transistor over the capacitor. The capacitor includes a first conductor, a first insulator, and a second conductor that are stacked in this order. The second conductor serves as one of a source and a drain of the second transistor. A third conductor functioning as the other of the source and the drain of the second transistor is located over the second insulator. An opening reaching the second conductor is provided in the second insulator and the third conductor. An oxide semiconductor, a third insulator, and a fourth conductor are stacked in this order to overlap with the opening. The fourth conductor is electrically connected to a source or a drain of the first transistor.

An electrostatic chuck member includes: a base body wherein one main surface thereof is a placement surface on which a plate-shaped sample is placed; and an electrostatic adsorption electrode provided on a side opposite to the placement surface or in the base body, in which a side peripheral surface that is continuous to the placement surface in the base body includes at least a first curved surface that is a convex surface and is provided in a circumferential direction in a peripheral portion of the placement surface and a second curved surface that is provided in the circumferential direction at a different height position from the first curved surface.

According to some embodiments of the present disclosure, methods of forming a semiconductor device on a semiconductor layer having opposing first and second surfaces are disclosed. An n-type doped region including an n-type dopant may be formed at the first surface of the semiconductor layer. A p-type dopant source layer including a p-type dopant may be formed on the n-type doped region. The p-type dopant may be diffused from the p-type dopant source layer through the n-type doped region into the semiconductor layer to form a p-type doped region of the semiconductor layer, and the p-type doped region of the semiconductor layer may be between the n-type doped region and the second surface of the semiconductor layer. After diffusing the p-type dopant, the p-type dopant source layer may be removed.