A method for growing a III-V material may include forming at least one layer on a stack including a crystalline layer made of III-V material, a first masking layer surmounting the germination layer, the first masking layer having at least one first opening; depositing a second masking layer covering an upper face of the sacrificial layer; forming at least one second opening in the second masking layer; removing the sacrificial layer selectively at the first masking layer and at the second masking layer; epitaxially growing a material made of the III-V material from the germination layer; forming al least one third opening in the second masking layer; and epitaxially growing at least one material made of the III-V material from the first epitaxial layer.

Solar cell structures comprising a plurality of solar cells, wherein each solar cell is separated from adjacent solar cell via a tunnel junction and/or a resonant tunneling structure (RTS), are described. Solar cells are implemented on Ge, Si, GaN, sapphire, and glass substrates. Each of the plurality of solar cells is at least partially constructed from a cell material which harnesses photons having energies in a predetermined energy range. In one embodiment each solar cell comprises of at least two sub-cells. It also describes a nano-patterned region/layer to implement high efficiency tandem/multi-junction solar cells that reduces dislocation density due to mismatch in lattice constants in the case of single crystalline and/or polycrystalline solar cells. Finally, solar structure could be used as light-emitting diodes when biased in forward biasing mode. The mode of operation could be determined by a programmed microprocessor.

In.sub.xAl.sub.yGa.sub.1-x-yN semiconductor structures having optoelectronic elements characterized by epitaxial layers having different in-plane a-lattice parameters and different InN mole fractions are disclosed. The active regions are configured to emit radiation in different wavelength ranges and are characterized by strain states within about 1% to 2% of compressive strain. The epitaxial layers are grown on patterned In.sub.xAl.sub.yGa.sub.1-x-yN seed regions on a single substrate, where the relaxed InGaN growth layers provide (0001) In.sub.xAl.sub.yGa.sub.1-x-yN growth surfaces characterized by different in-plane a-lattice parameters and different InN mole fractions. In.sub.xAl.sub.yGa.sub.1-x-yN semiconductor structures can be used in optoelectronic devices such as in light sources for illumination and in display applications.

Bulk relaxed Wurtzite In-containing III-nitride layers having a smooth and substantially pit-free surface morphology and an interface region having a substantially relaxed in-plane a-lattice parameter and characterized by a single-phase gallium-polar (0001) orientation are disclosed. Methods of making the bulk relaxed Wurtzite In-containing III-nitride layers using MOCVD growth conditions are also disclosed. Semiconductor structures include epitaxial layers grown on a bulk relaxed Wurtzite In-containing III-nitride layer. The semiconductor structures can be used in optoelectronic devices such as in light sources for illumination and display applications.

A method of fabricating semiconducting tellurium (Te) nanomesh. The method includes the steps of preparing a substrate, vaporizing Te powders under a first temperature; and growing Te nanomesh on the substrate using the vaporized Te powders under a second temperature. The first temperature is higher than the second temperature. The rationally designed nanomesh exhibits exciting properties, such as micrometer-level patterning capacity, excellent field-effect hole mobility, fast photoresponse in the optical communication region, and controllable electronic structure of the mixed-dimensional heterojunctions.