An apparatus configured to reduce lag includes a substrate; a group III-Nitride back barrier layer on the substrate; a group III-Nitride channel layer on the group III-Nitride back barrier layer; a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer include a higher bandgap than a bandgap of the group III-Nitride channel layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being arranged at or below the group III-Nitride barrier layer. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.

A silicon carbide semiconductor device has a cell region that includes a main cell region, a sense cell region, and an element isolation region electrically separating the main cell region and the sense cell region. The element isolation region includes a plurality of isolation trenches and a plurality of isolation deep layers of a second conductivity type. The isolation trenches are disposed between the main cell region and the sense cell region, and extend deeper than a base layer to separate the base layer into a section adjacent to the main cell region and a section adjacent to the sense cell region. The isolation deep layers are respectively disposed at bottom portions of the isolation trenches in contact with bottom surfaces of the isolation trenches.

A semiconductor substrate of a reverse conducting IGBT includes a collector layer in contact with a collector electrode, within an IGBT region and a boundary region. The collector layer has a first collector layer provided in the IGBT region and a second collector layer provided in the boundary region. The second collector layer has a lower impurity concentration than the first collector layer.

Disclosed are a Schottky diode and a manufacturing method thereof. The Schottky diode includes a substrate, a first semiconductor layer, a heterostructure layer, a passivation layer, and a cap layer stacked in sequence. The passivation layer includes a first groove and a second groove, and the first groove and the second groove penetrate through at least the passivation layer. A first electrode is arranged at least on the cap layer corresponding to the first groove; a second electrode is arranged in the second groove. A Schottky contact is formed between the first electrode and the cap layers, so that a direct contact area between the first electrode and the heterostructure layer may be avoided, a contradiction between the forward turn-on voltage and the reverse leakage of the Schottky diode may be balanced, and a leakage characteristic of the heterostructure layer in a high temperature environment may be suppressed.

A circuit device includes core circuitry. The circuit device further includes a first plurality of guard rings having a first dopant type, wherein the first plurality of guard rings is around a periphery of the core circuitry. The circuit device further includes a second plurality of guard rings having a second dopant type, wherein the second dopant type is opposite to the first dopant type, and at least one guard ring of the second plurality of guard rings is around a periphery of at least one guard ring of the first plurality of guard rings. Guard rings of the first plurality of guard rings are in a concentric arrangement.

A reverse-conducting insulated gate bipolar transistor (IGBT) includes a first conductivity type boundary layer of a first conductivity type and a second conductivity type boundary layer of a second conductivity type disposed in a boundary region located between an IGBT region and a diode region. The first conductivity type boundary layer is disposed below a drift layer, and is in contact with a lower electrode. The second conductivity type boundary layer is disposed between the first conductivity type boundary layer and the drift layer.

A semiconductor substrate of a reverse conducting IGBT has a first conductivity type buffer layer disposed between a collector layer and a drift layer. The buffer layer has a first buffer layer provided in the IGBT region and a second buffer layer provided in the boundary region. The peak concentration of the first conductivity type impurity in the second buffer layer is higher than that in the first buffer layer.

A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.

A method of manufacturing a transfer die for use in a transfer print process. The manufactured transfer die comprises a semiconductor device suitable for bonding to a silicon-on-insulator wafer. The method comprises the steps of providing a non-conductive isolation region in a semiconductor stack, the semiconductor stack comprising a sacrificial layer above a substrate; and etching an isolation trench into the semiconductor stack from an upper surface thereof, such that the isolation trench extends only to a region of the semiconductor stack above the sacrificial layer. The isolation trench and the non-conductive isolation region together separate a bond pad from a waveguide region in the optoelectronic device.

A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.