A microelectronic device comprises a stack structure, a contact structure, a liner material, and a boron-containing material. The stack structure comprises alternating conductive structures and dielectric structures. The contact structure extends through the stack structure. The liner material is between the stack structure and the contact structure. The boron-containing material is between the liner material and the stack structure. Related electronic systems and methods are also described.

A method of patterning a substrate includes exposing a photoresist layer on the substrate with a pattern of actinic radiation to form a chemically reactive surface pattern, and coating, at the track system, a spin-on-material to convert the chemically reactive surface pattern to a photoresist surface mask pattern. The method further includes etching the photoresist layer using the photoresist surface mask pattern as a first etch mask to form a photoresist mask pattern, and etching a layer to be etched with the photoresist mask pattern as a second etch mask.

A semiconductor device including an interleaved/nested structure of subtractive interconnects and damascene interconnects. The semiconductor device includes a subtractive-etched interconnect wiring level having subtractive interconnects and a damascene interconnect wiring level having damascene interconnects. The subtractive-etched interconnect wiring level includes first electrodes that have a first potential second electrodes that have a second potential different from the first potential, with the second electrodes generated to interleave the first electrodes. The semiconductor also includes a damascene interconnect wiring level that includes other first electrodes having the first potential, and other second electrodes having the second potential. In the damascene interconnect wiring level, the other second electrodes are also interleaved by the other first electrodes.

A method and apparatus for processing a semiconductor is disclosed herein. In one embodiment, a processing system for semiconductor processing is disclosed. The processing chamber includes two transfer chambers, a processing chamber, and a rotation module. The processing chamber is coupled to the transfer chamber. The rotation module is positioned between the transfer chambers. The rotation module is configured to rotate the substrate. The transfer chambers are configured to transfer the substrate between the processing chamber and the transfer chamber. In another embodiment, a method for processing a substrate on the apparatus is disclosed herein.

A method includes depositing a dielectric layer over a semiconductor substrate; forming a first photoresist layer over the dielectric layer; patterning the first photoresist layer to form through holes, such that a first portion of the first photoresist layer between a first one and a second one of the through holes has a less height than a second portion of the first photoresist layer between the first one and a third one of the through holes; forming a spacer on the first portion of the first photoresist layer; performing an etching process on the dielectric layer to form via holes while the spacer remains covering the first portion of the first photoresist layer; forming a plurality of metal vias in the via holes.