The present disclosure discloses a method and apparatus for manufacturing a microfluidic chip with a femtosecond plasma grating. The method is characterized in that two or more beams of femtosecond pulse laser act on quartz glass together at a certain included angle and converge in the quartz glass, and when pulses achieve synchronization in time domain, the two optical pulses interfere; Benefited by constraint of an interference field, only one optical filament is formed in one interference period; and numbers of optical filaments are arranged equidistantly in space to form the plasma grating. The apparatus for manufacturing the microfluidic chip includes a plasma grating optical path, a microchannel processing platform, and a hydrofluoric acid ultrasonic cell.

In an embodiment a device includes a substrate including an upper substrate surface and a lower substrate surface and a membrane-layer suspended above the upper substrate surface, wherein the substrate includes a recess penetrating the substrate between the lower substrate surface and the upper substrate surface, wherein the membrane-layer spans the recess, wherein the recess includes an upper recess region, an intermediate recess region, and a lower recess region, wherein the upper recess region is a part of the recess in direct vicinity to the upper substrate surface, the intermediate recess region is a part of the recess directly below the upper recess region, and the lower recess region is a part of the recess other than the upper recess region and the intermediate recess region, and wherein a cross-sectional area of the upper recess region determined parallel to the upper substrate surface is larger than a respective cross-sectional area of the intermediate recess region.

A semiconductor device comprises a structured metal layer. The structured metal layer lies above a semiconductor substrate. In addition, a thickness of the structured metal layer is more than 100 nm. Furthermore, the semiconductor device comprises a covering layer. The covering layer lies adjacent to at least one part of a front side of the structured metal layer and adjacent to a side wall of the structured metal layer. In addition, the covering layer comprises amorphous silicon carbide.

A preclean process may be omitted from a eutectic bonding sequence. To remove oxide from one or more surfaces of a device wafer of a micro-electromechanical-system (MEMS) structure, a duration of an acid-based etch process in the eutectic bonding sequence may be increased relative to the duration of the acid-based etch process when the preclean process is performed. The increased duration of the acid-based etch process enables the acid-based etch process to remove the oxide from the one or more surfaces of the device wafer without the use of a preceding preclean process. This reduces the complexity and cycle time of the eutectic bonding sequence, reduces the risk of stiction between suspended mechanical components of the MEMS structure, and/or reduces the likelihood that the MEMS structure may be rendered defective or inoperable during manufacturing, which increases process yield.

A semiconductor substrate includes a first semiconductor layer, a first dielectric layer coupled to the first semiconductor layer, and a second semiconductor layer coupled to the first dielectric layer. The second semiconductor layer includes a base portion substantially aligned with the first dielectric layer and a cantilever portion protruding from an end of the first dielectric layer. The cantilever portion includes a tapered surface tapering from a bottom surface of the second semiconductor layer toward a top surface of the second semiconductor layer.

A preclean process may be omitted from a eutectic bonding sequence. To remove oxide from one or more surfaces of a device wafer of a micro-electromechanical-system (MEMS) structure, a duration of an acid-based etch process in the eutectic bonding sequence may be increased relative to the duration of the acid-based etch process when the preclean process is performed. The increased duration of the acid-based etch process enables the acid-based etch process to remove the oxide from the one or more surfaces of the device wafer without the use of a preceding preclean process. This reduces the complexity and cycle time of the eutectic bonding sequence, reduces the risk of stiction between suspended mechanical components of the MEMS structure, and/or reduces the likelihood that the MEMS structure may be rendered defective or inoperable during manufacturing, which increases process yield.

The present invention relates to the field of semiconductor technology and provides a method for forming an MEMS cavity structure, which can improve process yield for MEMS integration and encapsulation for functional stability and reliability of the MEMS structure. The method includes steps of: forming an adhesion material layer on a bottom layer; forming a bottom layer on a substrate; forming a adhesion material layer on the bottom layer; forming a support structure and a sacrificial layer that is filled in a space surrounded by the support structure on the adhesion material layer; forming a capping layer on the support structure and the sacrificial layer, and the bottom layer, the support structure and the capping layer together defining a cavity; and releasing the sacrificial layer and the adhesion material layer to form the cavity structure.

A patterning method of a film is disclosed. The method including: providing a film including a first surface; forming n etching barrier layers on the first surface of the film, and n is an integer larger than or equal to 2; and performing n etching processes on the film to form a recessed structure on the first surface using the n etching barrier layers as masks, the recessed structure includes n bottom surfaces respectively having different depths. Two adjacent etching processes of the n etching processes include a previous etching process and a subsequent etching process, and after the previous etching process is completed, a part of the n etching barrier layers is removed to form a mask for the subsequent etching process; a material of the part of the n etching barrier layers which is removed is different from a material of the mask of the subsequent etching process.

A semiconductor oxide plate is formed on a recessed surface in a semiconductor matrix material layer. Comb structures are formed in the semiconductor matrix material layer. The comb structures include a pair of inner comb structures spaced apart by a first semiconductor portion. A second semiconductor portion that laterally surrounds the first semiconductor portion is removed selective to the comb structures using an isotropic etch process. The first semiconductor portion is protected from an etchant of the isotropic etch process by the semiconductor oxide plate, the pair of inner comb structures, and a patterned etch mask layer that covers the comb structures. A movable structure for a MEMS device is formed, which includes a combination of the first portion of the semiconductor matrix material layer and the pair of inner comb structures.

Provided is a gas sensor including a substrate, a first membrane disposed on the substrate, a heating structure disposed on the first membrane, a second membrane disposed on the heating structure, a sensing electrode disposed on the second membrane, and a sensing material structure disposed on the sensing electrode. Here, the substrate provides an isolation space defined by a recessed surface obtained as a portion of a top surface of the substrate is spaced downward from a bottom surface of the first membrane, and the first membrane provides a first membrane etching hole that vertically extends to connect a top surface and the bottom surface of the first membrane and is connected with the isolation space. Also, the first membrane etching hole has a diameter of about 3 μm to about 20 μm.