A liquid ejection head includes a recording element substrate including an ejection port member including a liquid ejection port, an electrical wiring layer including a pressure generating element that pressurizes the liquid to eject the liquid and an electrically connecting part connected to the pressure generating element to supply power for driving the pressure generating element to the pressure generating element, and a silicon substrate having the ejection port member and the electrical wiring layer. The silicon substrate includes a through-hole passing through the silicon substrate to expose the electrically connecting part. An outer shape of an opening of the through-hole on the back side of the silicon substrate has no side parallel to direction [110] of the silicon substrate or has a side parallel to the direction [110]. The side has a length equal to or less than half an entire length of the through-hole in the direction [110].

There are provided a head chip, a liquid jet head, a liquid jet recording device, and a method of manufacturing the head chip each capable of preventing the short circuit of electrodes by ink to maintain an excellent ejection performance over a long period of time. The head chip according to an aspect of the present disclosure includes an actuator plate, a cover plate, and an intermediate plate. In the actuator plate, open apertures which communicate an inside and an outside of a non-ejection channel with each other are formed in both end portions of the non-ejection channel in a Y direction. In the actuator plate, open apertures which communicate an inside and an outside of a non-ejection channel with each other are formed in both end portions of the non-ejection channel in the Y direction.

A wafer structure is disclosed and includes a chip substrate and plural inkjet chips having plural ink-drip generators. Each ink-drop generator includes a thermal-barrier layer, a resistance heating layer and a protective layer. The thermal-barrier layer is formed on the chip substrate, the resistance heating layer is formed on the thermal-barrier layer, a part of the protective layer is formed on the resistance heating layer, and the barrier layer is formed on the protective layer. The ink-supply chamber has a bottom in communication with the protective layer, and a top in communication with the nozzle. The thermal-barrier layer has a thickness of 500˜5000 angstroms, the protective layer has a thickness of 150˜3500 angstroms, the resistance heating layer has a thickness of 100˜500 angstroms, the resistance heating layer has a length of 5˜30 microns, and the resistance heating layer has a width of 5˜10 microns.

A wafer structure is disclosed and includes a chip substrate and at least one inkjet chip having plural ink-drip generators. Each ink-drop generator includes a thermal-barrier layer, a resistance heating layer and a protective layer. The thermal-barrier layer is formed on the chip substrate, the resistance heating layer is formed on the thermal-barrier layer, a part of the protective layer is formed on the resistance heating layer, and the barrier layer is formed on the protective layer. The ink-supply chamber has a bottom in communication with the protective layer, and a top in communication with the nozzle. The thermal-barrier layer has a thickness of 500˜5000 angstroms, the protective layer has a thickness of 150˜3500 angstroms, the resistance heating layer has a thickness of 100˜500 angstroms, the resistance heating layer has a length of 5˜30 microns, and the resistance heating layer has a width of 5˜10 microns.

A wafer structure is disclosed and includes a chip substrate and an inkjet chip. The chip substrate is a silicon substrate fabricated by a semiconductor process on a wafer of 12 inches. The inkjet chips are formed on the chip substrate by the semiconductor process and diced into the inkjet chip. The inkjet chip includes plural ink-drop generators generated by the semiconductor process on the chip substrate. Each of the plurality of ink-drop generators includes a nozzle. A diameter of the nozzle is in a range between 0.5 micrometers and 10 micrometers. A volume of an inkjet drop discharged from the nozzle is in a range between 1 femtoliter and 3 picoliters. The ink-drop generators form plural longitudinal axis array groups having a pitch and plural horizontal axis array groups having a central stepped pitch equal to or less than 1/600 inches.

An improved photoimageable dry film formulation, a fluidic ejection head containing a thick film layer derived from the improved photoimageable dry film formulation, and a method for making a fluidic ejection head. The improved photoimageable dry film formulation includes a multifunctional epoxy compound, a photoinitiator capable of generating a cation, a non-photoreactive solvent, and from about 0.5 to about 5% by weight a silane oligomer adhesion enhancer based on a total weight of the photoimageable dry film formulation before drying.

A wafer structure is disclosed and includes a chip substrate and plural inkjet chips having plural ink-drip generators. Each ink-drop generator includes a thermal-barrier layer, a resistance heating layer and a protective layer. The thermal-barrier layer is formed on the chip substrate, the resistance heating layer is formed on the thermal-barrier layer, a part of the protective layer is formed on the resistance heating layer, and the barrier layer is formed on the protective layer. The ink-supply chamber has a bottom in communication with the protective layer, and a top in communication with the nozzle. The thermal-barrier layer has a thickness of 500˜5000 angstroms, the protective layer has a thickness of 150˜3500 angstroms, the resistance heating layer has a thickness of 100˜500 angstroms, the resistance heating layer has a length of 5˜30 microns, and the resistance heating layer has a width of 5˜10 microns.

A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate fabricated by a semiconductor process. At least one inkjet chip is directly formed on the chip substrate by the semiconductor process and diced into the at least one inkjet chip for inkjet printing. Each of the inkjet chip includes a plurality of ink-drop generators produced by a semiconductor process and formed on the chip substrate. Each of the ink-drop generators includes a thermal-barrier layer, a resistance heating layer, a conductive layer, a protective layer, a barrier layer, an ink-supply chamber and a nozzle.

A wafer structure is disclosed and includes a chip substrate and at least one inkjet chip. The chip substrate is a silicon substrate which is fabricated by a semiconductor process on a wafer of at least 12 inches. The at least one inkjet chip is directly formed on the chip substrate by the semiconductor process, and the wafer is diced into the at least one inkjet chip, to be implemented for inkjet printing.

A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate which is fabricated by a semiconductor process on a wafer of at least 12 inches. The plurality of inkjet chips include at least one first inkjet chip and at least one second inkjet chip. The plurality of inkjet chips are directly formed on the chip substrate by the semiconductor process, respectively, and diced into the at least one first inkjet chip and the at least one second inkjet chip, to be implemented for inkjet printing. Each of the first inkjet chip and the second inkjet chip includes a plurality of ink-drop generators produced by the semiconductor process and formed on the chip substrate.