An integrated circuit to drive a plurality of fluid actuation devices includes an interface, a digital circuit, an analog circuit, and control logic. The digital circuit outputs a digital signal to the interface. The analog circuit outputs an analog signal to the interface. The control logic activates the digital circuit or the analog circuit.

An integrated circuit to drive a plurality of fluid actuation devices includes a configuration register, a plurality of interfaces, and control logic. The plurality of interfaces include a mode interface and a data interface. The control logic enables writing to the configuration register in response to a signal on the mode interface transitioning to logic high with a logic high signal on the data interface.

In some examples, a fluid dispensing device component includes a plurality of fluidic dies each comprising a memory, a plurality of control inputs to provide respective control information to respective fluidic dies of the plurality of fluidic dies, and a data bus connected to the plurality of fluidic dies, the data bus to provide data of the memories of the plurality of fluidic dies to an output of the fluid dispensing device component.

The present subject matter relates to disposing memory banks and select register. In an example implementation, a plurality of memory banks is arranged to form a group of memory banks. Each memory bank includes a plurality of memory units. At least one select register generates a select signal to access the memory units in the plurality of memory banks. The at least one select register is disposed at an end of the group of memory banks.

A fluidic die includes a sense architecture having a global sense block to provide an analog reference signal and an array of distributed sense blocks. Each distributed sense block is to receive a same set of addresses via an address bus and each is to receive a corresponding sense enable signal having an enable value or a disable value. Each distributed sense block includes an array of sensors, each sensor corresponding to a different address of the set of addresses and a sample circuit to apply the analog reference signal to the sensor corresponding to the address on the address bus when the corresponding sense enable signal has the enable value, and provide to the global sense block an analog sense signal from the sensor resulting from application of the analog reference signal.

A printer head controller includes memory for storing command configuration information for a packet to be transmitted to a printer head, memory for storing print data to be transmitted to the printer head, and memory for storing printing parameters for the printer head. A command get circuit acquires commands included in the command configuration information. A data get circuit acquires the print data from the memory when a print command is in the configuration information and setting data from the memory when a setting command is in the command configuration information. A generation circuit generates the packets including the command(s) and data associated with the command(s) as acquired by the data get circuit.

A droplet ejecting device includes: a head including N-number drive elements; a driving circuit including N-number waveform signal selectors and N-number power supply circuit selectors; a plurality of power supply circuits connected to the driving circuit; and a control circuit. Each waveform signal selector selects a waveform signal to be outputted to the corresponding drive element from among a plurality of types of waveform signals. Each power supply circuit selectors selects a power supply circuit to be connected to the drive elements from among the plurality of power supply circuits. The control circuit serially transmits, to the driving circuit via a single control line: N-number items of waveform signal designation information each of which designates the waveform signal to be outputted to the corresponding drive element; and N-number items of power supply designation information each of which designates the power supply circuit to be connected to the corresponding drive element.

A fluid ejection device may include a substrate, a first group of fluid drivers on the substrate, a second group of fluid drivers on the substrate, a memory element storing a predetermined offset value and electronics to receive an address of one of the fluid drivers of the first group for actuation control. The electronics may select one of the fluid drivers of the second group for actuation control based on the address and the stored offset value.

An element substrate according to an embodiment of the present invention includes a plurality of print elements and a plurality of drive elements for driving the plurality of print elements. The element substrate comprises a generation circuit configured to generate a first drive signal that drives drive elements belonging to a first group among the plurality of drive elements, and a second drive signal that drives drive elements belonging to a second group among the plurality of drive elements, using a selector configured to switch a signal transmitted from outside of the element substrate and an output destination of the signal within one block period in driving the plurality of drive elements by dividing the plurality of elements into the plurality of blocks. The first drive signal and the second drive signal are generated at different timings.

A shift circuit operating by using a capacitor, a printing head and printing device thereof. The shift circuit includes a power signal line, a grounding signal line, a first shift signal line, a second shift signal line, a plurality of diodes, a plurality of grounding resistors, a plurality of thyristors, a cascaded resistor and a capacitor. The capacitor connects between the gate of the first thyristor and the first shift signal line. Therefore, the capacitor is charged during the off time of the period of the first clock signal, and starts to be discharged from an edge between the on time and the off time of the period of the first clock signal. During the on time of the period, the capacitor is fully discharged. Such that, the gate voltage of the first thyristor is sufficient to turn on the first thyristor and will not affect the following shift action.