The present invention provides a novel method of constructing a coax spring-pin socket that furnishes better performance and is easier to manufacture in volume using common dielectrics and copper plating. This is accomplished by, in application, a lamination of PCB dielectric layers. This dielectric block is then drilled, plated, etched, and drilled in steps for the construction of a coaxial structure for the signal pins, and a ground structure for ground pins. This design process that can be quickly adjusted and customized for each design.

The present invention provides a novel method of constructing a coax spring-pin socket that furnishes better performance and is easier to manufacture in volume using common dielectrics and copper plating. This is accomplished by, in application, a lamination of PCB dielectric layers. This dielectric block is then drilled, plated, etched, and drilled in steps for the construction of a coaxial structure for the signal pins, and a ground structure for ground pins. This design process that can be quickly adjusted and customized for each design.

A panel-shaped metal wall grids array for panel level IC packaging and associated manufacturing method. Each metal wall grid in the metal wall grids array has a continuous and closed metal wall of a predetermined wall height. The metal wall grids are connected to form a monolithic panel through a plurality of metal connecting portions. When the panel-shaped metal wall grids array is used for panel level IC packaging, at least one IC chip/IC die is disposed in each metal wall grid with a top surface of each IC chip/IC die facing downwards, and a panel-shaped metal layer matching with the panel-shaped wall grids array may be further formed on the entire back side of the panel-shaped metal wall grids array so that the panel-shaped metal layer is bonded to the metal wall of each metal wall grid.

Sequential electrodeposition of metals into through-mask features on a semiconductor substrate is conducted such as to reduce the deleterious consequences of lipseal's pressure onto the mask material. In a first electroplating step, a first metal (e.g., nickel) is electrodeposited using a lipseal that has an innermost point of contact with the semiconductor substrate at a first distance from the edge of the substrate. In a second electroplating step, a second metal (e.g., tin) is electrodeposited using a lipseal that has an innermost point of contact with the semiconductor substrate at a greater distance from the edge of the substrate than the first distance. This allows to at least partially shift the lipseal pressure from a point that could have been damaged during the first electrodeposition step and to shield from electrolyte any cracks that might have formed in the mask material during the first electroplating step.

Provided is a wetting method for substrate that allows reducing an amount of air bubbles attached to a surface to be plated with a simple structure.

The wetting method for substrate includes a holding step 102 of holding a back surface of a substrate with a back plate such that a surface to be plated of the substrate is opposed to a liquid surface of a plating solution housed in a plating tank, a supplying step 104 of supplying the plating solution to the plating tank such that the plating solution upwardly flows through a plurality of through-holes in a center part of an ionically resistive element arranged inside the plating tank to raise a center part of the liquid surface of the plating solution, a first lowering step 106 of lowering a supporting member for supporting an outer edge portion of the surface to be plated of the substrate held by the holding member toward the liquid surface of the plating solution, and a second lowering step 108 of lowering the holding member such that the substrate is sandwiched by the supporting member lowered in the first lowering step 106 and the holding member while the center part of the liquid surface of the plating solution is raised in the supplying step 104.

Provided is a wetting method for substrate that allows reducing an amount of air bubbles attached to a surface to be plated with a simple structure.

The wetting method for substrate includes a holding step 102 of holding a back surface of a substrate with a back plate such that a surface to be plated of the substrate is opposed to a liquid surface of a plating solution housed in a plating tank, a supplying step 104 of supplying the plating solution to the plating tank such that the plating solution upwardly flows through a plurality of through-holes in a center part of an ionically resistive element arranged inside the plating tank to raise a center part of the liquid surface of the plating solution, a first lowering step 106 of lowering a supporting member for supporting an outer edge portion of the surface to be plated of the substrate held by the holding member toward the liquid surface of the plating solution, and a second lowering step 108 of lowering the holding member such that the substrate is sandwiched by the supporting member lowered in the first lowering step 106 and the holding member while the center part of the liquid surface of the plating solution is raised in the supplying step 104.

Provided are an electronic component manufacturing method by which even a platable layer made of a difficult-to-plate material can be easily plated with good adhesion without using a special chemical solution or a photolithography technique, and an electronic component which has a peel strength of 0.1 N/mm or greater as measured by a copper foil peel test. A picosecond laser beam having a pulse duration on the order of a picosecond or a femtosecond laser beam having a pulse duration on the order of a femtosecond is emitted at a surface of a platable layer (2) in order to roughen the surface, a wiring pattern is formed using a mask (13), and a plated part (12) is formed on the surface of the wiring pattern.

A device includes a dielectric layer having a first surface and a second surface. The device also includes a first set of high-aspect ratio electroplated structures disposed on the first surface of the dielectric layer and a second set of high-aspect ratio electroplated structures disposed on the second surface of the dielectric layer opposite the first set of high-aspect ratio electroplated structures.

A device includes a dielectric layer having a first surface and a second surface. The device also includes a first set of high-aspect ratio electroplated structures disposed on the first surface of the dielectric layer and a second set of high-aspect ratio electroplated structures disposed on the second surface of the dielectric layer opposite the first set of high-aspect ratio electroplated structures.

Iridium electroplating compositions containing 1,10-phenanthroline compounds in trace amounts to electroplate substantially defect-free uniform and smooth surface morphology indium on metal layers. The indium electroplating compositions can be used to electroplate indium metal on metal layers of various substrates such as semiconductor wafers and as thermal interface materials.