Nanotwinned copper and non-nanotwinned copper may be electroplated to form mixed crystal structures such as 2-in-1 copper via and RDL structures or 2-in-1 copper via and pillar structures. Nanotwinned copper may be electroplated on a non-nanotwinned copper layer by pretreating a surface of the non-nanotwinned copper layer with an oxidizing agent or other chemical reagent. Alternatively, nanotwinned copper may be electroplated to partially fill a recess in a dielectric layer, and non-nanotwinned copper may be electroplated over the nanotwinned copper to fill the recess. Copper overburden may be subsequently removed.

An encapsulated polymeric article is disclosed. The encapsulated polymeric article may include a polymer substrate and a metallic outer shell at least partially encapsulating the polymer substrate. The encapsulated polymeric article may be fabricated by a method comprising: 1) providing a mandrel in a shape of the encapsulated polymeric article, 2) shaping the metallic outer shell on the mandrel, 3) removing the mandrel from the metallic outer shell, and 4) molding the polymeric substrate into the metallic outer shell through a port formed in the metallic outer shell to provide the encapsulated polymeric article.

In some examples, a system comprises a die having multiple electrical connectors extending from a surface of the die and a lead coupled to the multiple electrical connectors. The lead comprises a first conductive member; a first non-solder metal plating stacked on the first conductive member; an electroplated layer stacked on the first non-solder metal plating; a second non-solder metal plating stacked on the electroplated layer; and a second conductive member stacked on the second non-solder metal plating, the second conductive member being thinner than the first conductive member. The system also comprises a molding to at least partially encapsulate the die and the lead.

The present disclosure provides a method for producing a wiring substrate. A seeded substrate is first prepared. The seeded substrate includes an insulation substrate, a conductive undercoat layer having a hydrophilic surface and provided on the insulation substrate, a conductive seed layer provided on a first region of the surface of the undercoat layer, the first region having a predetermined pattern, and a water-repellent layer on the second region of the surface of the undercoat layer, the second region being a region other than the first region. Subsequently, a metal layer is formed on the seed layer. A voltage is applied between the anode and the seed layer while a solid electrolyte membrane being disposed between the seeded substrate and the anode, and the solid electrolyte membrane and the seed layer being pressed into contact with each other. Thereafter, the water-repellent layer and the undercoat layer are etched.

The present disclosure provides a method for producing a wiring substrate. A seeded substrate is first prepared. The seeded substrate includes an insulation substrate, a conductive undercoat layer having a hydrophilic surface and provided on the insulation substrate, a conductive seed layer provided on a first region of the surface of the undercoat layer, the first region having a predetermined pattern, and a water-repellent layer on the second region of the surface of the undercoat layer, the second region being a region other than the first region. Subsequently, a metal layer is formed on the seed layer. A voltage is applied between the anode and the seed layer while a solid electrolyte membrane being disposed between the seeded substrate and the anode, and the solid electrolyte membrane and the seed layer being pressed into contact with each other. Thereafter, the water-repellent layer and the undercoat layer are etched.

Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject matter further discloses methods of electrolytic plating by controlling surface area of an anode.

An interconnect structure of a semiconductor device includes a conductive via and a barrier layer lining an interface between a dielectric layer and the conductive via. The barrier layer is selectively deposited along sidewalls of a recess formed in a dielectric layer. The conductive via is formed by selectively electroplating electrically conductive material such as rhodium, iridium, or platinum in an opening of the recess, where the conductive via is grown upwards from an exposed metal surface at a bottom of the recess. The conductive via includes an electrically conductive material having a low electron mean free path, low electrical resistivity, and high melting point. The interconnect structure of the semiconductor device has reduced via resistance and improved resistance to electromigration and/or stress migration.

The present invention relates to the use of an aqueous composition comprising tin ions optionally further alloy metal ions selected from silver, copper, indium, and bismuth ions and at least one additive comprising a linear or branched polyimidazolium compound comprising the structural unit of formula (L1) for depositing tin or tin alloy containing layers and a process for depositing tin alloy layer onto a substrate. ##STR00001##

The present invention relates to the use of an aqueous composition comprising tin ions optionally further alloy metal ions selected from silver, copper, indium, and bismuth ions and at least one additive comprising a linear or branched polyimidazolium compound comprising the structural unit of formula (L1) for depositing tin or tin alloy containing layers and a process for depositing tin alloy layer onto a substrate. ##STR00001##

Provided is an apparatus for electro-forming. The apparatus for electro-forming includes a plating bath which is a space where a substrate is plated and a clamp disposed within the plating bath and configured to grasp the substrate disposed in a horizontal direction. The apparatus for electro-forming further includes an assembly including an anode spaced above the substrate and connected to an external power supply and a plating solution supply unit spaced above the substrate and configured to supply a plating solution. The apparatus for electro-forming also includes a driving unit configured to reciprocate the assembly in a horizontal direction at a distance from the substrate. The assembly further includes an insulator between the anode and the plating solution supply unit.