A silicon-carbide volume monocrystal is produced with a specific electrical resistance of at least 10.sup.5 Ωcm. An SiC growth gas phase is generated in a crystal growing area of a crucible. The SiC volume monocrystal grows by deposition from the SiC growth gas phase. The growth material is transported from a supply area inside the growth crucible to a growth boundary surface of the growing monocrystal. Vanadium is added to the crystal growing area as a doping agent. A temperature at the growth boundary surface is set to at least 2250° C. and the SiC volume monocrystal grows doped with a vanadium doping agent concentration of more than 5.Math.10.sup.17 cm.sup.−3. The transport of material from the SiC supply area to the growth boundary surface is additionally influenced. The growing temperature at the growth boundary surface and the material transport to the growth boundary surface are influenced largely independently of one another.

A silicon-carbide volume monocrystal is produced with a specific electrical resistance of at least 10.sup.5 Ωcm. An SiC growth gas phase is generated in a crystal growing area of a crucible. The SiC volume monocrystal grows by deposition from the SiC growth gas phase. The growth material is transported from a supply area inside the growth crucible to a growth boundary surface of the growing monocrystal. Vanadium is added to the crystal growing area as a doping agent. A temperature at the growth boundary surface is set to at least 2250° C. and the SiC volume monocrystal grows doped with a vanadium doping agent concentration of more than 5.Math.10.sup.17 cm.sup.−3. The transport of material from the SiC supply area to the growth boundary surface is additionally influenced. The growing temperature at the growth boundary surface and the material transport to the growth boundary surface are influenced largely independently of one another.

An SiC crystal (10) has Fe concentration not higher than 0.1 ppm and Al concentration not higher than 100 ppm. A method of manufacturing an SiC crystal includes the following steps. SiC powders for polishing are prepared as a first source material (17). A first SiC crystal (11) is grown by sublimating the first source material (17) through heating and precipitating an SiC crystal. A second source material (12) is formed by crushing the first SiC crystal (11). A second SiC crystal (14) is grown by sublimating the second source material (12) through heating and precipitating an SiC crystal. Thus, an SiC crystal and a method of manufacturing an SiC crystal capable of achieving suppressed lowering in quality can be obtained.

An SiC crystal (10) has Fe concentration not higher than 0.1 ppm and Al concentration not higher than 100 ppm. A method of manufacturing an SiC crystal includes the following steps. SiC powders for polishing are prepared as a first source material (17). A first SiC crystal (11) is grown by sublimating the first source material (17) through heating and precipitating an SiC crystal. A second source material (12) is formed by crushing the first SiC crystal (11). A second SiC crystal (14) is grown by sublimating the second source material (12) through heating and precipitating an SiC crystal. Thus, an SiC crystal and a method of manufacturing an SiC crystal capable of achieving suppressed lowering in quality can be obtained.

Various embodiments provide for systems and techniques for the successful fabrication of metal oxide (TMO)-on-glass layer stacks via direct deposition. The resulting samples feature epitaxial, strontium titanate (STO) or barium titanate (BTO) films on silicon dioxide (SiO.sub.2) layers, forming STO- or BTO-buffered SiO.sub.2 pseudo-substrates. As the integration of TMO films on silicon rely on an STO or BTO buffer layer, a wide variety of TMO-based integrated devices (e.g., circuits, waveguides, etc.) can be fabricated from the TMO-on-glass platform of the present technology. Moreover, the STO, or the BTO, survives the fabrication process without a corresponding degradation of crystalline quality, as evidenced by various objective measures.

A method is disclosed for making semiconductor films from a eutectic alloy comprising a metal and a semiconductor. Through heterogeneous nucleation said film is deposited at a deposition temperature on relatively inexpensive buffered substrates, such as glass. Specifically said film is vapor deposited at a fixed temperature in said deposition temperature where said deposition temperature is above a eutectic temperature of said eutectic alloy and below a temperature at which the substrate softens. Such films could have widespread application in photovoltaic and display technologies.

Disclosed is a process of surface treatment of a substrate. The method of treating a surface of a substrate comprises preparing the substrate, and performing an etching process with respect to a surface of the substrate. The etching process comprises a step of introducing etching gas to the surface of the substrate, and the etching gas comprises a halogen compound and a silane compound.

A silicon carbide substrate has a first main surface, and a second main surface opposite to the first main surface. A region including at least one main surface of the first and second main surfaces is made of single-crystal silicon carbide. In the one main surface, sulfur atoms are present at not less than 60×10.sup.10 atoms/cm.sup.2 and not more than 2000×10.sup.10 atoms/cm.sup.2, and carbon atoms as an impurity are present at not less than 3 at % and not more than 25 at %. Thereby, a silicon carbide substrate having a stable surface, a semiconductor device using the substrate, and methods for manufacturing them can be provided.

A Group III nitride substrate contains a base material part of a Group III nitride having a front surface and a back surface, the front surface of the base material part and the back surface of the base material part having different Mg concentrations from each other.

Thin freestanding nitride veneers can be used for the fabrication of semiconductor devices. These veneers are typically less than 100 microns thick. The use of thin veneers also eliminates the need for subsequent wafer thinning for improved thermal performance and 3D packaging.