Process of surface treatment for wafer

Abstract

Disclosed is a process of surface treatment of a substrate. The method of treating a surface of a substrate comprises preparing the substrate, and performing an etching process with respect to a surface of the substrate. The etching process comprises a step of introducing etching gas to the surface of the substrate, and the etching gas comprises a halogen compound and a silane compound.

Claims

1. A process of surface treatment for a substrate, the method comprising: preparing the substrate; and etching a surface of the substrate, wherein etching the surface of the substrate comprises: forming an oxide layer on the substrate; introducing etching as to the surface of the substrate; and performing a dry etching or a wet etching process with respect to the surface of the substrate, wherein the substrate comprises a silicon carbide substrate, and wherein the etching gas comprises a halogen compound and a silane compound.

2. The process of claim 1, wherein the halogen compound comprises hydrogen chloride (HCl).

3. The process of claim 1, wherein the silane compound comprises at least one selected from the group consisting of SiHx (x is an integer of 1 to 4), methylchlorosilane (MTS), and tetratrichlorosilane (TCS).

4. The process of claim 1, wherein the silane compound is introduced at a mole ratio in a range of 0.01 to 1 based on the halogen compound.

5. The process of claim 1, wherein the etching gas is introduced at a temperature of 1100° C. to 1650° C.

6. A method of fabricating an epitaxial wafer, the method comprising: preparing a substrate; etching a surface of the substrate; and growing an epitaxial layer from the substrate, wherein etching a surface of the substrate comprises: forming an oxide layer on the substrate; introducing etching gas to the surface of the substrate; and performing a dry etching or a wet etching process with respect to the surface of the substrate, wherein the substrate comprises a silicon carbide substrate, and wherein the etching gas comprises a halogen compound and a silane compound.

7. The method of claim 6, wherein the halogen compound comprises hydrogen chloride (HCl).

8. The method of claim 6, wherein the silane compound comprises at least one selected from the group consisting of SiHx (x is an integer of 1 to 4), methylchlorosilane (MTS), and tetratrichlorosilane (TCS).

9. The method of claim 6, wherein the silane compound is introduced at a mole ratio in a range of 0.01 to 1 based on the halogen compound.

10. The method of claim 6, wherein the etching gas is introduced at a temperature of 1100° C. to 1650° C.

11. The method of claim 6, wherein the epitaxial layer comprises silicon carbide (SiC).

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a view showing molecular bonding representing surface defects created due to the excessive extraction of Si according to an HCl etching scheme according to the related art;

(2) FIG. 2 is a flowchart showing the process of the surface treatment for a substrate according to the embodiment;

(3) FIG. 3 is a view showing molecular bonding representing the removal of the surface defect resulting from the complementation of Si according to the process of the surface treatment for the substrate according to the embodiment; and

(4) FIG. 4 is a flowchart showing a method of fabricating an epitaxial wafer according to the embodiment.

MODE FOR THE INVENTION

(5) In the description of the embodiments, it will be understood that, when a layer (or film), a region, a pattern, or a structure is referred to as being “on” or “under” another substrate, another layer (or film), another region, another pad, or another pattern, it can be “directly” or “indirectly” on the other substrate, layer (or film), region, pad, or pattern, or one or more intervening layers may also be present. Such a position of the layer has been described with reference to the drawings.

(6) The thickness and size of each a layer (or film), each region, each pattern, or each structure shown in the drawings may be exaggerated, omitted or schematically drawn for the purpose of convenience or clarity. In addition, the size of the layer (or film), the region, the pattern, or the structure does not utterly reflect an actual size.

(7) Hereinafter, the embodiment of the disclosure will be described in detail with reference to accompanying drawings.

(8) FIG. 2 is a flowchart showing the process of the surface treatment for a wafer according to the embodiment.

(9) Referring to FIG. 2, the process of the surface treatment for a wafer according to the embodiment comprises a step of preparing a substrate (step ST10) and a step of performing an etching process with respect to the surface of the substrate (step ST20). The etching process comprises a step of introducing the etching gas to the surface of the substrate. The etching gas comprises a halogen compound and a silane compound.

(10) According to the step of preparing the substrate (step ST10), a wafer may be prepared. The wafer may comprise a silicon carbide wafer. In addition, the wafer may comprise a silicon carbide wafer before an epitaxial layer is grown.

(11) The wafer may have defects on the surface thereof. The defects may protrude from the surface of the wafer. The defects increase the surface roughness of the wafer to significantly exert a bad influence to the following processes. The surface defects on the wafer may cause another defect when the epitaxial layer is grown, so that the epitaxial layer has a rough surface.

(12) According to the etching process (step ST20), the etching gas may be introduced to the surface of the wafer. In other words, in order to remove the surface defect of the wafer, an oxide layer is formed on the wafer, and a dry etching process or a wet etching process is performed with respect to the wafer, so that the defects can be removed from the wafer surface.

(13) The etching gas may comprise both of a halogen compound and a silane compound. The halogen compound may comprise hydrogen chloride (HCl) gas. The silane compound may comprise SiH.sub.x, methylchlorosilane (MTS), or tetratrichlorosilane (TCS). In SiH.sub.x, x represents the range of 1 to 4. In other words, the SiHx may comprise silane-based compounds in an instable state to a stable state.

(14) Regarding the introduction ratio of a silane compound to a halogen compound, wherein the silane compound is introduced at a mole ratio in a range of 0.01 to 1 based on the halogen compound. The introduction ratio of the silane compound may be varied according to the extraction degree of Si extracted through the etching process of the halogen compound, that is, HCl.

(15) In addition, the reaction temperature at which the introduced etching gas reacts to the surface of the wafer may be in the range of 1100° C. to 1650° C. Preferably, the reaction temperature may be in the range of 1175° C. or 1650° C.

(16) FIG. 3 is a view showing that the halogen compound and the silane compound, which have been introduced to the surface of the wafer, react to the surface of the wafer.

(17) Referring to FIG. 3, the halogen compound and the silane compound are introduced to the surface of the wafer to extract and complement silicon (Si) on the wafer. In other words, silicon (Si) protruding from the surface of the wafer may be etched. In addition, SiHx may complement silicon (Si) that have been excessively etched by HCl.

(18) According to the related art, as shown in FIG. 1, the HCl etching is excessively performed, so that silicon (Si) are excessively extracted. Accordingly, etch-pit may be created in the wafer to cause another defects.

(19) However, in the process of the surface treatment for the wafer according to the embodiment, a silane compound is introduced together with HCl so that silicon (Si) can be complemented. Accordingly, defects having higher energy can be removed from the wafer, so that the wafer can have low defects having stable low energy.

(20) The epitaxial layer grown from the wafer having low defects may have a lower defect density, and the device employing the epitaxial wafer can represent higher electrical characteristics.

(21) FIG. 4 is a flowchart showing a method of fabricating an epitaxial wafer according to the embodiment.

(22) Referring to FIG. 4, the method of fabricating the epitaxial layer according to the embodiment comprises a step of preparing a substrate (step ST30), a step of performing an etching process with respect to the surface of the substrate (step ST40), and a step of growing an epitaxial layer on the substrate (step ST50). The etching process comprises a step of introducing the etching gas to the surface of the substrate. The etching gas comprises a halogen compound and a silane compound.

(23) As described above, the etching gas may comprise both of a halogen compound and a silane compound. The halogen compound may comprise hydrogen chloride (HCl) gas. The silane compound may comprise SiHx, methylchlorosilane (MTS), or tetratrichlorosilane (TCS). In SiH.sub.x, x represents the range of 1 to 4. In other words, the SiH.sub.x may comprise silane-based compounds in an instable state to a stable state.

(24) Regarding the introduction ratio of a silane compound to a halogen compound, wherein the silane compound is introduced at a mole ratio in a range of 0.01 to 1 based on the halogen compound. The introduction ratio of the silane compound may be varied according to the extraction degree of Si extracted through the etching process of the halogen compound, that is, HCl.

(25) Accordingly, the halogen compound and the silane compound are introduced to the surface of the wafer to extract and complement silicon (Si) on the wafer. Therefore, according to the epitaxial wafer fabricated according to the fabrication method, the epitaxial layer can be grown from the wafer having a flat surface without the surface defects through the etching process. Therefore, when the device employing the epitaxial wafer is used, superior electrical characteristics can be represented.

(26) Any reference in this specification to “one embodiment,” “an embodiment,” “example embodiment,” etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is comprised in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other ones of the embodiments.

(27) Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.