There is provided a nitride semiconductor template, including: a substrate having a front surface and a back surface opposite to the front surface; a back side semiconductor layer provided on a back surface side of the substrate, comprising a polycrystalline group III nitride semiconductor, and having a linear expansion coefficient different from a linear expansion coefficient of the substrate; and a front side semiconductor layer provided on a front surface side of the substrate, comprising a monocrystalline group III nitride semiconductor, and having a linear expansion coefficient different from a linear expansion coefficient of the substrate, wherein a thickness of the front side semiconductor layer is a thickness exceeding a critical thickness at which cracks are generated in the front side semiconductor layer when only the front side semiconductor layer is formed without forming the back side semiconductor layer.

In a method for using a sputtering target, by making an ion collide with the sputtering target, a sputtered particle whose size is greater than or equal to 1/3000 and less than or equal to 1/20, preferably greater than or equal to 1/1000 and less than or equal to 1/30 of a crystal grain is generated.

There is provided a piezoelectric film, being a polycrystalline film comprised of potassium sodium niobate; containing at least one metal element selected from a group consisting of Cu and Mn; and having 1.0 or less ratio of a concentration B of the metal element at grain boundaries of crystals, with respect to a concentration A of the metal element in a matrix phase of the crystals.

There is provided a piezoelectric film, being a polycrystalline film comprised of potassium sodium niobate; containing at least one metal element selected from a group consisting of Cu and Mn; and having 1.0 or less ratio of a concentration B of the metal element at grain boundaries of crystals, with respect to a concentration A of the metal element in a matrix phase of the crystals.

A support substrate 2 is a polycrystalline SiC substrate formed of polycrystalline SiC. Assuming that one of the two sides of the polycrystalline SiC substrate is a first side and that the other side is a second side, a substrate grain size change rate of the polycrystalline SiC substrate, which is a value obtained by dividing a difference between the average value of crystal grain sizes of the polycrystalline SiC on the first side and the average value of crystal grain sizes of the polycrystalline SiC on the second side by a thickness of the polycrystalline SiC substrate, is 0.43% or less. A radius of curvature of warpage of the polycrystalline SiC substrate is 142 m or more.

A support substrate 2 is a polycrystalline SiC substrate formed of polycrystalline SiC. Assuming that one of the two sides of the polycrystalline SiC substrate is a first side and that the other side is a second side, a substrate grain size change rate of the polycrystalline SiC substrate, which is a value obtained by dividing a difference between the average value of crystal grain sizes of the polycrystalline SiC on the first side and the average value of crystal grain sizes of the polycrystalline SiC on the second side by a thickness of the polycrystalline SiC substrate, is 0.43% or less. A radius of curvature of warpage of the polycrystalline SiC substrate is 142 m or more.

There is provided a nitride semiconductor template, including: a substrate having a front surface and a back surface opposite to the front surface; a back side semiconductor layer provided on a back surface side of the substrate, comprising a polycrystalline group III nitride semiconductor, and having a linear expansion coefficient different from a linear expansion coefficient of the substrate; and a front side semiconductor layer provided on a front surface side of the substrate, comprising a monocrystalline group III nitride semiconductor, and having a linear expansion coefficient different from a linear expansion coefficient of the substrate, wherein a thickness of the front side semiconductor layer is a thickness exceeding a critical thickness at which cracks are generated in the front side semiconductor layer when only the front side semiconductor layer is formed without forming the back side semiconductor layer.

There is provided a nitride semiconductor template, including: a substrate having a front surface and a back surface opposite to the front surface; a back side semiconductor layer provided on a back surface side of the substrate, comprising a polycrystalline group III nitride semiconductor, and having a linear expansion coefficient different from a linear expansion coefficient of the substrate; and a front side semiconductor layer provided on a front surface side of the substrate, comprising a monocrystalline group III nitride semiconductor, and having a linear expansion coefficient different from a linear expansion coefficient of the substrate, wherein a thickness of the front side semiconductor layer is a thickness exceeding a critical thickness at which cracks are generated in the front side semiconductor layer when only the front side semiconductor layer is formed without forming the back side semiconductor layer.

To enhance piezoelectric property. One aspect of the present invention is ferroelectric ceramics including a Pb(Zr.sub.1-xTi.sub.x)O.sub.3 film, wherein: the x satisfies the following formula 1, the Pb(Zr.sub.1-xTi.sub.x)O.sub.3 film has a plurality of columnar single crystals, the x axis, the y axis and the z axis of each of the plurality of columnar single crystals are oriented in the same direction, respectively,
0<x<1formula 1.

The upper electrode 31 has a hole 35 extending from an upper surface 33 to a lower surface 34, a bolt 36 is inserted from the upper surface 33 of the upper electrode 31 into the hole 35, and secured in a lower electrode 32 by a screw. A gap 51 between an inside of the hole 35 and a straight body portion of the bolt 36 allows the upper electrode 31 to slide in all directions in a placement surface (upper surface of the lower electrode 32 in contact with the lower surface 34 of the upper electrode 31 in FIG. 2) that is a contact surface with an upper surface of the lower electrode 32, thereby providing an effect of preventing occurrence of a crack or a break in a U rod that can be expanded and contracted in all directions during a vapor phase growth process.