A method for clonal-growth of a single-crystal metal, including: using copper as an example, placing an existing small-sized single-crystal copper foil with a plane of any index on a copper foil that needs to be single-crystallized, and performing annealing to obtain, by cloning, a large-area (in meters) single-crystal copper foil with the same surface index as that of the parent facet. The method solves the difficult problem of large-area single-crystal copper foil preparation. By performing annealing, a parent single-crystal copper foil with a very small size (˜0.25 cm.sup.2) can be cloned to produce a large-area (˜700 cm.sup.2) single-crystal copper foil, which is an increase in area of about 3000 times.

A method for clonal-growth of a single-crystal metal, including: using copper as an example, placing an existing small-sized single-crystal copper foil with a plane of any index on a copper foil that needs to be single-crystallized, and performing annealing to obtain, by cloning, a large-area (in meters) single-crystal copper foil with the same surface index as that of the parent facet. The method solves the difficult problem of large-area single-crystal copper foil preparation. By performing annealing, a parent single-crystal copper foil with a very small size (˜0.25 cm.sup.2) can be cloned to produce a large-area (˜700 cm.sup.2) single-crystal copper foil, which is an increase in area of about 3000 times.

A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

Provided are a structure for producing a high-quality single crystal diamond, and a method for manufacturing the structure for producing diamond. A structure for producing a diamond is composed of a base substrate and an Ir thin film formed on the base substrate. The thermal expansion coefficient of the base substrate is 5 times or less of the thermal expansion coefficient of diamond and the melting point of the base substrate is 700° C. or higher. The peak angle in the X-ray diffraction pattern of the Ir thin film is different from the peak angle in the X-ray diffraction pattern of the base substrate.

The present disclosure generally relates to compositions comprising substrate-free crystalline 2D bismuthene, and the method of making and using the substrate-free crystalline 2D bismuthene.

A method for deposition of a thin film onto a substrate is provided. The method includes providing a source precursor containing on or more of elements constituting the thin film, generating a transient species from the source precursor, and depositing a thin film onto the substrate from the transient species. The transient species being a reactive intermediate that has a limited lifetime in a condensed phase at or above room temperature.

A method for deposition of a thin film onto a substrate is provided. The method includes providing a source precursor containing on or more of elements constituting the thin film, generating a transient species from the source precursor, and depositing a thin film onto the substrate from the transient species. The transient species being a reactive intermediate that has a limited lifetime in a condensed phase at or above room temperature.

The present invention provides a control method to epitaxial growth monolayer graphene, in which a monolayer graphene is epitaxially grown on a non-polar crystal face at arbitrary angle of a non-polar crystal face SiC substrate, thereby utilizing the non-polar crystal face to manipulate the electrical transport properties of graphene. A monolayer graphene having ballistic transport properties can be epitaxially grown at arbitrary angle of non-polar crystal face SiC substrate by the above-mentioned control method.

The present invention provides a control method to epitaxial growth monolayer graphene, in which a monolayer graphene is epitaxially grown on a non-polar crystal face at arbitrary angle of a non-polar crystal face SiC substrate, thereby utilizing the non-polar crystal face to manipulate the electrical transport properties of graphene. A monolayer graphene having ballistic transport properties can be epitaxially grown at arbitrary angle of non-polar crystal face SiC substrate by the above-mentioned control method.