Nano-wire growth processes, nano-wires, and articles having nano-wires are disclosed. The nano-wire growth process includes trapping growth-inducing particles on a substrate, positioning the substrate within a chamber, closing the chamber, applying a vacuum to the chamber, introducing a precursor gas to the chamber, and thermally decomposing the precursor gas. The thermally decomposing of the precursor gas grows nano-wires from the growth-inducing particles. The nano-wires and the articles having the nano-wires are produced by the nano-wire growth process.

A method of forming an oxide film is provided. The method may include: supplying mist of a solution including a material of the oxide film dissolved therein to a surface of a substrate together with a carrier gas having an oxygen concentration equal to or less than 21 vol % so as to epitaxially grow the oxide film on the surface of the substrate; and bringing the oxide film into contact with a fluid comprising oxygen atoms after the epitaxial growth of the oxide film.

A method for increasing the conductivity of a metal oxide with crystal structure belonging to the 4/m 32/m point group is provided. Single crystal oxides with crystal structure belonging to 4/m 32/m point group are contacted with nitrogen gas, with oxygen gas, with nitrogen gas, with oxygen gas, then with nitrogen gas to increase the conductivity of the metal oxide with crystal structure belonging to the 4/m 32/m point group.

Reduced and low work function materials capable of optimizing electron emission performance in a range of vacuum and nanoscale electronic devices and processes and a method for reducing work function and producing reduced and low work function materials are described. The reduced and low work function materials advantageously may be made from single crystal materials, preferably metals, and from amorphous materials with optimal thicknesses for the materials. A surface geometry is created that may significantly reduce work function and produce a reduced or low work function for the material. It is anticipated that low and ultra-low work function materials may be produced by the present invention and that these materials will have particular utility in the optimization of electron emissions in a wide range of vacuum microelectronics and other nanoscale electronics and processes.

Semiconductor wafers useful for NAND circuitry and having a front side, a rear side, a middle and a periphery, have an Nv region which extends from the middle to the periphery; a denuded zone which extends from the front side to a depth of not less than 20 m into the interior of the semiconductor wafer, where the density of vacancies in the denuded zone, determined by means of platinum diffusion and DLTS is not more than 110.sup.13 vacancies/cm.sup.3; a concentration of oxygen of not less than 4.510.sup.17 atoms/cm.sup.3 and not more than 5.510.sup.17 atoms/cm.sup.3; a region in the interior of the semiconductor wafer which adjoins the denuded zone and has nuclei which can be developed by means of a heat treatment into BMDs having a peak density of not less than 6.010.sup.9/cm.sup.3, where the heat treatment comprises heating the semiconductor wafer to a temperature of 800 C. over a period of four hours and to a temperature of 1000 C. over a period of 16 hours. The wafers are produced by a unique RTA treatment of Nv wafers.

The disclosure is directed to a method to recover the gate oxide integrity yield of a silicon wafer after rapid thermal anneal in an ambient atmosphere comprising a nitrogen containing gas, such as NH.sub.3 or N.sub.2. Generally, rapid thermal anneals in an ambient atmosphere comprising a nitrogen containing gas, such as NH.sub.3 or N.sub.2 to thereby imprint an oxygen precipitate profile can degrade the GOI yield of a silicon wafer by exposing as-grown crystal defects (oxygen precipitate) and vacancies generated by the silicon nitride film. The present invention restores GOI yield by stripping the silicon nitride layer, which is followed by wafer oxidation, which is followed by stripping the silicon oxide layer.

A device includes a semiconductor substrate containing gallium nitride and having a crystal face inclined from 0.05 to 15 inclusive with respect to the c-plane. The semiconductor substrate includes an irregular portion on the crystal face, and the contact angle of pure water having a specific resistance of 18 M.Math.cm or more on the surface of the irregular portion is 10 or less.

In an example, a method of manufacturing a semiconductor device includes providing a semiconductor substrate comprising an unpolished CZ silicon substrate, a substrate upper side, and a substrate lower side opposite to the substrate upper side. The method includes first annealing the semiconductor substrate at a first temperature in an inert environment for a first time. The method includes second annealing the semiconductor substrate at a second temperature in a wet oxidation environment for a second time. The first annealing dissolves inner wall oxide in bulk region voids and the second annealing fills the voids with semiconductor interstitials. In some examples, the CZ silicon substrate is provided from a CZ ingot grown in the presence of a magnetic field and using continuous counter-doping. The method provides, among other things, a CZ silicon substrate with reduced crystal originated particle (COP) defects, reduced oxygen concentration, and reduced radial resistivity variation.

A gallium arsenide single crystal substrate having a main surface, in which a ratio of the number of As atoms existing as diarenic trioxide to the number of As atoms existing as diarsenic pentoxide is greater than or equal to 2 when the main surface is measured by X-ray photoelectron spectroscopy, in which an X-ray having energy of 150 eV is used and a take-off angle of a photoelectron is set to 5. Arithmetic average roughness (Ra) of the main surface is less than or equal to 0.3 nm.

There are provided a setting process configured to set in a chamber an aluminum nitride substrate in which a semiconductor layer is formed on a first principal plane, and an oxide film forming process configured to heat an inside of the chamber with a water molecule (H.sub.2O) being introduced in the chamber and to form an oxide film including an amorphous oxide film and/or a crystalline oxide film on a second principal plane located on an opposite side to the first principal plane of the aluminum nitride substrate.