A method for heat-treating a silicon single crystal wafer by an RTA treatment, including: putting a silicon single crystal wafer having an Nv region for the entire plane of the silicon single crystal wafer or an Nv region containing an OSF region for the silicon single crystal wafer entire plane into an RTA furnace, performing pre-heating at temperature lower than temperature at which silicon reacts with NH3 while supplying gas that contains NH3 into the RTA furnace, subsequently stopping the supply of the gas containing NH3 and starting supply of Ar gas to start an RTA treatment under Ar gas atmosphere in which the NH3 gas remains. This provide a method for heat-treating a silicon single crystal wafer that give gettering capability without degrading TDDB properties even to a silicon single crystal wafer in which the entire plane is an Nv region or an Nv region containing an OSF region.

Suitability of silicon wafers for use in device processing without generation of fatal defects is assessed by using SIRD to measure stress in a wafer cut from a piece of a crystal ingot after first and second thermal treatments of the water, the second thermal treatment consisting of a heating phase, a holding phase, and a cooling phase. The result is used to consider whether silicon wafers cut from the piece can adequately survive device processing without generating excess defects.

Suitability of silicon wafers for use in device processing without generation of fatal defects is assessed by using SIRD to measure stress in a wafer cut from a piece of a crystal ingot after first and second thermal treatments of the water, the second thermal treatment consisting of a heating phase, a holding phase, and a cooling phase. The result is used to consider whether silicon wafers cut from the piece can adequately survive device processing without generating excess defects.

A method of oxidation-combusting an ingot grower comprises a) blocking between the filter housing and the exhaust pipe, b) forming the filter housing in a vacuum state, and c) injecting air into the filter housing through an injection pipe connected to a first side of the filter housing to combust the filter housing.

The invention relates to scintillation inorganic oxide single crystals with garnet structure, which comprise cerium and are co-alloyed with titanium and Group 2 elements. The invention makes it possible to increase the scintillation output and to enhance the energy resolution of scintillation detectors during gamma-ray quantum registration. The technical result is achieved by a single crystal with a garnet structure being co-alloyed with cerium, titanium and Group 2 elements. This single crystal is produced by the Czochralski process.

The invention relates to scintillation inorganic oxide single crystals with garnet structure, which comprise cerium and are co-alloyed with titanium and Group 2 elements. The invention makes it possible to increase the scintillation output and to enhance the energy resolution of scintillation detectors during gamma-ray quantum registration. The technical result is achieved by a single crystal with a garnet structure being co-alloyed with cerium, titanium and Group 2 elements. This single crystal is produced by the Czochralski process.

A method for preparing suspended graphene support film by selectively etching growth substrate is disclosed in present invention. The transfer process of graphene is avoided. The process of present invention is efficient and low in cost, suspended graphene support film can be prepared in a single etching step. The prepared graphene support film does not need any support by polymer film and polymer fiber. The prepared graphene support film has controllable number of layers and high intactness (90%-97%), large suspended area (diameter is 10-50 μm), wide clean area (>100 nm) and can be mass-produced. In addition, the graphene support film can be directly used as transmission electron microscope support film, and can be used to achieve high resolution imaging of nanoparticles.

Provided is a SiC composite substrate including a biaxially-oriented SiC layer in which SiC is oriented in both a c-axis direction and an a-axis direction, and a SiC polycrystalline layer provided on one surface of the biaxially-oriented SiC layer. A joint interface of the biaxially-oriented SiC layer and the SiC polycrystalline layer has an uneven shape, which has an amount of unevenness of 1 to 200 μm.

A method for manufacturing a silicon single crystal wafer for a multilayer structure device including: using a silicon single crystal wafer with oxygen concentration of 12 ppma (JEITA) or higher and composing an N.sub.v region; and performing an RTA treatment in a nitrogen-containing atmosphere and a temperature of 1225° C. or higher, a mirror-polish processing treatment, and a BMD-forming heat treatment manufacturing a silicon single crystal wafer having at least a DZ layer with a thickness of 5 to 12.5 μm and a BMD layer positioned immediately below the DZ layer and a BMD density of 1×10.sup.11/cm.sup.3 or higher from the silicon single crystal wafer surface. During device formation, the silicon wafer surface stress is absorbed immediately below a surface layer, distortion defects are absorbed by the BMD layer, device formation region strength is enhanced, and surface layer dislocation occurrence and extension is suppressed.

A method for manufacturing a silicon single crystal wafer for a multilayer structure device including: using a silicon single crystal wafer with oxygen concentration of 12 ppma (JEITA) or higher and composing an N.sub.v region; and performing an RTA treatment in a nitrogen-containing atmosphere and a temperature of 1225° C. or higher, a mirror-polish processing treatment, and a BMD-forming heat treatment manufacturing a silicon single crystal wafer having at least a DZ layer with a thickness of 5 to 12.5 μm and a BMD layer positioned immediately below the DZ layer and a BMD density of 1×10.sup.11/cm.sup.3 or higher from the silicon single crystal wafer surface. During device formation, the silicon wafer surface stress is absorbed immediately below a surface layer, distortion defects are absorbed by the BMD layer, device formation region strength is enhanced, and surface layer dislocation occurrence and extension is suppressed.