C30B33/02

SILICON CARBIDE SINGLE CRYSTAL WAFER, CRYSTAL, PREPARATION METHODS THEREFOR, AND SEMICONDUCTOR DEVICE

A silicon carbide single crystal wafer and a preparation method therefor, a silicon carbide crystal and a preparation method therefor, and a semiconductor device. The surface of the silicon carbide single crystal wafer is such that an included angle between a normal direction and a c direction is 0-8 degrees, and aggregated dislocations on the silicon carbide single crystal wafer are less than 300/cm.sup.2; the aggregated dislocation is a dislocation aggregated condition in which the distance between the geometric centers of any two corrosion pits in the corrosion pits obtained after corrosion of melted KOH is less than 80 microns. Even if the dislocation density is relatively high, the aggregated dislocation density is relatively small, thereby increasing the yield of a silicon carbide-based devices.

Electric field driven assembly of ordered nanocrystal superlattices

An electric field drives nanocrystals dispersed in solvents to assemble into ordered three-dimensional superlattices. A first electrode and a second electrode 214 are in the vessel. The electrodes face each other. A fluid containing charged nanocrystals fills the vessel between the electrodes. The electrodes are connected to a voltage supply which produces an electrical field between the electrodes. The nanocrystals will migrate toward one of the electrodes and accumulate on the electrode producing ordered nanocrystal accumulation that will provide a superlattice thin film, isolated superlattice islands, or coalesced superlattice islands.

Electric field driven assembly of ordered nanocrystal superlattices

An electric field drives nanocrystals dispersed in solvents to assemble into ordered three-dimensional superlattices. A first electrode and a second electrode 214 are in the vessel. The electrodes face each other. A fluid containing charged nanocrystals fills the vessel between the electrodes. The electrodes are connected to a voltage supply which produces an electrical field between the electrodes. The nanocrystals will migrate toward one of the electrodes and accumulate on the electrode producing ordered nanocrystal accumulation that will provide a superlattice thin film, isolated superlattice islands, or coalesced superlattice islands.

METHODS FOR FORMING AN EPITAXIAL WAFER
20220359195 · 2022-11-10 ·

Methods for preparing epitaxial wafers are disclosed. The methods may involve control of the (i) a growth velocity, v, and/or (ii) an axial temperature gradient, G, during the growth of an ingot segment such that v/G is less than a critical v/G. An epitaxial layer is deposited on a substrate sliced from the silicon ingot.

Nitride semiconductor template and nitride semiconductor device

There is provided a method for manufacturing a nitride semiconductor template constituted by forming a nitride semiconductor layer on a substrate, comprising: (a) forming a first layer by epitaxially growing a nitride semiconductor containing aluminum on the substrate; (b) applying annealing to the first layer in an inert gas atmosphere; and (c) forming a second layer by epitaxially growing a nitride semiconductor containing aluminum on the first layer by a vapor phase growth after performing (b), and constituting the nitride semiconductor layer by the first layer and the second layer.

Nitride semiconductor template and nitride semiconductor device

There is provided a method for manufacturing a nitride semiconductor template constituted by forming a nitride semiconductor layer on a substrate, comprising: (a) forming a first layer by epitaxially growing a nitride semiconductor containing aluminum on the substrate; (b) applying annealing to the first layer in an inert gas atmosphere; and (c) forming a second layer by epitaxially growing a nitride semiconductor containing aluminum on the first layer by a vapor phase growth after performing (b), and constituting the nitride semiconductor layer by the first layer and the second layer.

NITRIDE SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR ELEMENT, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE
20230100683 · 2023-03-30 · ·

A nitride semiconductor substrate (11, 21) includes: a substrate (2); and an AlN-containing film (100, 200) provided above the substrate (2). A thickness of the AlN-containing film (100, 200) is at most 10000 nm, and a threading dislocation density of the AlN-containing film (100, 200) is at most 2×10.sup.8 cm.sup.−2.

Synthetic single crystal diamond

Provided is a synthetic single crystal diamond containing nitrogen atoms at a concentration of more than 600 ppm and 1500 ppm or less. The Raman shift λ′ (cm.sup.−1) of a peak in a primary Raman scattering spectrum of the synthetic single crystal diamond and the Raman shift λ (cm.sup.−1) of a peak in a primary Raman scattering spectrum of a synthetic type IIa single crystal diamond containing nitrogen atoms at a content of 1 ppm or less satisfy the following expression (1):
λ′−λ≥−0.10  (1).

Synthetic single crystal diamond

Provided is a synthetic single crystal diamond containing nitrogen atoms at a concentration of more than 600 ppm and 1500 ppm or less. The Raman shift λ′ (cm.sup.−1) of a peak in a primary Raman scattering spectrum of the synthetic single crystal diamond and the Raman shift λ (cm.sup.−1) of a peak in a primary Raman scattering spectrum of a synthetic type IIa single crystal diamond containing nitrogen atoms at a content of 1 ppm or less satisfy the following expression (1):
λ′−λ≥−0.10  (1).

METHOD FOR PRODUCING A SEMICONDUCTOR WAFER COMPOSED OF MONOCRYSTALLINE SILICON
20220349089 · 2022-11-03 ·

A method produces a single-crystal silicon semiconductor wafer. A single-crystal silicon substrate wafer is double side polished. A front side of the substrate wafer is chemical mechanical polished (CMP). An epitaxial layer of single-crystal silicon is deposited on the front side of the substrate wafer. A first rapid thermal anneal (RTA) treatment is performed on the coated substrate wafer at 1275-1295° C. for 15-30 seconds in argon and oxygen, having oxygen of 0.5-2.0 vol %. The coated substrate wafer is then cooled at or below 800° C., with 100 vol % argon. A second RTA treatment is performed on the coated substrate wafer at a 1280-1300° C. for 20-35 seconds in argon. An oxide layer is removed from a front side of the coated substrate wafer. The front side of the coated substrate wafer is polished by CMP.