Patent classifications
C30B33/08
Thallium bromide (TIBr) semiconductors and devices with extended life apparatus, methods, and system
Various technologies pertaining to formation or treatment of a thallium bromide crystal to improve the operable lifespan of a device that incorporates the thallium bromide crystal are described herein. In exemplary embodiments, treatments including focused ion beam implantation, selective material removal, and buffer layer application are performed on a thallium bromide crystal to inhibit motion of dislocations toward a region at which an electrical contact is desirably installed. In other exemplary embodiments, a thallium bromide crystal is doped with impurities during formation that inhibit the motion of dislocations in the crystal. In still other exemplary embodiments, a thallium bromide crystal is formed by way of processes that inhibit dislocation formation during crystal growth or eliminate dislocations in an existing thallium bromide mass.
Thallium bromide (TIBr) semiconductors and devices with extended life apparatus, methods, and system
Various technologies pertaining to formation or treatment of a thallium bromide crystal to improve the operable lifespan of a device that incorporates the thallium bromide crystal are described herein. In exemplary embodiments, treatments including focused ion beam implantation, selective material removal, and buffer layer application are performed on a thallium bromide crystal to inhibit motion of dislocations toward a region at which an electrical contact is desirably installed. In other exemplary embodiments, a thallium bromide crystal is doped with impurities during formation that inhibit the motion of dislocations in the crystal. In still other exemplary embodiments, a thallium bromide crystal is formed by way of processes that inhibit dislocation formation during crystal growth or eliminate dislocations in an existing thallium bromide mass.
LITHIATION OF POROUS-Si FOR HIGH PERFORMANCE ANODE
An element to be used as an anode in a lithium-ion battery comprising a lithiated single crystal porous-silicon layer made on the surface of a p-doped single crystal Si of thickness 25-1000 mm and resistivity of less than 0.01-ohm cm. Successful lithiation is achieved either electrochemically or by direct alloying of lithium metal with the porous-Si with a wide range of porosities. The lithiated silicon anode allows a high cathode loading in a lithium-ion battery resulting in record current densities without the formation of lithium dendrites.
LITHIATION OF POROUS-Si FOR HIGH PERFORMANCE ANODE
An element to be used as an anode in a lithium-ion battery comprising a lithiated single crystal porous-silicon layer made on the surface of a p-doped single crystal Si of thickness 25-1000 mm and resistivity of less than 0.01-ohm cm. Successful lithiation is achieved either electrochemically or by direct alloying of lithium metal with the porous-Si with a wide range of porosities. The lithiated silicon anode allows a high cathode loading in a lithium-ion battery resulting in record current densities without the formation of lithium dendrites.
LAYERED GaAs, METHOD OF PREPARING SAME, AND GaAs NANOSHEET EXFOLIATED FROM SAME
The present invention relates to: layered gallium arsenide (GaAs), which is more particularly layered GaAs, which, unlike the conventional bulk GaAs, has a two-dimensional crystal structure, has the ability to be easily exfoliated into nanosheets, and exhibits excellent electrical properties by having a structure that enables easy charge transport in the in-plane direction; a method of preparing the same; and a GaAs nanosheet exfoliated from the same.
Process for producing semiconductor wafers
Semiconductor wafers are produced by a process wherein a single-crystal ingot of semiconductor material is pulled and at least one wafer is removed from the ingot, wherein the wafer is subjected to a thermal treatment comprising a heat treatment step in which a radial temperature gradient acts on the wafer, wherein an analysis of the wafer of semiconductor material with respect to the formation of defects in the crystal lattice, so-called stress fields, is carried out.
Process for producing semiconductor wafers
Semiconductor wafers are produced by a process wherein a single-crystal ingot of semiconductor material is pulled and at least one wafer is removed from the ingot, wherein the wafer is subjected to a thermal treatment comprising a heat treatment step in which a radial temperature gradient acts on the wafer, wherein an analysis of the wafer of semiconductor material with respect to the formation of defects in the crystal lattice, so-called stress fields, is carried out.
SILICON CARBIDE SUBSTRATE AND METHOD OF MANUFACTURING SILICON CARBIDE SUBSTRATE
A silicon carbide substrate includes a first main surface, a second main surface, a threading screw dislocation, and a blind scratch. The second main surface is located opposite to the first main surface. The threading screw dislocation extends to each of the first main surface and the second main surface. The blind scratch is exposed at the first main surface and extends linearly as viewed in a direction perpendicular to the first main surface. A value obtained by dividing an area density of the blind scratch by an area density of threading screw dislocation is smaller than 0.13.
Group 13 element nitride wafer with reduced variation in off-cut angle
The invention relates to a two-dimensional crystal wafer of group 13 or III element nitride which is delimited by a face of orientation N, an opposing face of orientation E depending on the group 13 or III element, E being selected preferably from Ga, In, Al or a combination of these elements, characterized in that the variation in crystalline off-cut angle in the largest dimension of said wafer is less than 5?10-3?/mm, and its curvature of geometric deformation of its faces exhibits a flexure in terms of absolute value of less than 10-.sup.3 mm/mm of the largest dimension of said wafer.
Group 13 element nitride wafer with reduced variation in off-cut angle
The invention relates to a two-dimensional crystal wafer of group 13 or III element nitride which is delimited by a face of orientation N, an opposing face of orientation E depending on the group 13 or III element, E being selected preferably from Ga, In, Al or a combination of these elements, characterized in that the variation in crystalline off-cut angle in the largest dimension of said wafer is less than 5?10-3?/mm, and its curvature of geometric deformation of its faces exhibits a flexure in terms of absolute value of less than 10-.sup.3 mm/mm of the largest dimension of said wafer.