A method of a growing an embedded single crystal diamond structure, comprising: disposing a single crystal diamond on a non-diamond substrate, wherein the non-diamond substrate is larger than the single crystal diamond; masking a top portion of the single crystal diamond using a masking material; and using a chemical vapor deposition (CVD) growth chamber, growing polycrystalline diamond material surrounding the single crystal diamond in order to join the single crystal diamond to the polycrystalline diamond material.

A method of a growing an embedded single crystal diamond structure, comprising: disposing a single crystal diamond on a non-diamond substrate, wherein the non-diamond substrate is larger than the single crystal diamond; masking a top portion of the single crystal diamond using a masking material; and using a chemical vapor deposition (CVD) growth chamber, growing polycrystalline diamond material surrounding the single crystal diamond in order to join the single crystal diamond to the polycrystalline diamond material.

Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

Some examples herein provide a method of forming a doped silicon germanium layer. The method may include simultaneously exposing a substrate to (a) a silicon precursor, (b), a germanium precursor, (c) a boron precursor, and (d) a heteroleptic gallium precursor. The heteroleptic gallium precursor may include (i) at least one straight chain alkyl group in which a terminal carbon is directly bonded to gallium, and (ii) at least one tertiary alkyl group in which a tertiary carbon is directly bonded to gallium. The method may include reacting the silicon precursor, the germanium precursor, the boron precursor, and the heteroleptic gallium precursor to form a silicon germanium layer on the substrate that is doped with boron and gallium.

Some examples herein provide a method of forming a doped silicon germanium layer. The method may include simultaneously exposing a substrate to (a) a silicon precursor, (b), a germanium precursor, (c) a boron precursor, and (d) a heteroleptic gallium precursor. The heteroleptic gallium precursor may include (i) at least one straight chain alkyl group in which a terminal carbon is directly bonded to gallium, and (ii) at least one tertiary alkyl group in which a tertiary carbon is directly bonded to gallium. The method may include reacting the silicon precursor, the germanium precursor, the boron precursor, and the heteroleptic gallium precursor to form a silicon germanium layer on the substrate that is doped with boron and gallium.

Methods and systems for selectively forming crystalline boron-doped silicon germanium on a surface of a substrate. The methods can be used to selectively form the boron-doped silicon germanium within a gap from the bottom upward. Exemplary methods can be used to, for example, form source and/or drain regions in field effect transistor devices, such as in gate-all-around field effect transistor devices.

Methods and systems for selectively forming crystalline boron-doped silicon germanium on a surface of a substrate. The methods can be used to selectively form the boron-doped silicon germanium within a gap from the bottom upward. Exemplary methods can be used to, for example, form source and/or drain regions in field effect transistor devices, such as in gate-all-around field effect transistor devices.

The present invention relates to: layered gallium arsenide (GaAs), which is more particularly layered GaAs, which, unlike the conventional bulk GaAs, has a two-dimensional crystal structure, has the ability to be easily exfoliated into nanosheets, and exhibits excellent electrical properties by having a structure that enables easy charge transport in the in-plane direction; a method of preparing the same; and a GaAs nanosheet exfoliated from the same.

The present invention relates to: layered gallium arsenide (GaAs), which is more particularly layered GaAs, which, unlike the conventional bulk GaAs, has a two-dimensional crystal structure, has the ability to be easily exfoliated into nanosheets, and exhibits excellent electrical properties by having a structure that enables easy charge transport in the in-plane direction; a method of preparing the same; and a GaAs nanosheet exfoliated from the same.

A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.