According to one embodiment, an electronic device includes a base region, an element portion located on the base region, the element portion including a movable portion, and a protective film overlying the element portion and forming a cavity on an inner side of the protective film. The protective film includes a first protective layer and a second protective layer located on the first protective layer. A hole extends in a direction parallel to a main surface of the base region, and the second protective layer covers the hole.

A method for manufacturing semiconductor structure includes: providing a substrate having a first surface; forming a trench on the first surface, wherein a bottom surface and side walls of the substrate are configured along an outer periphery of the trench; annealing the substrate with high-purity argon or high-purity hydrogen to flatten the bottom surface and the side walls; conformally disposing a composite-material layer to cover the first surface, the bottom surface and the side walls; disposing a polysilicon material layer in the trench; removing the composite-material layer on the first surface; forming a multi-layer metal interconnection structure on the first surface and the polysilicon material layer, the multi-layer metal interconnection structure including a MEMS frame structure and through holes; removing the polysilicon material layer and the composite-material layer; using plasma treatment to the trench to flatten the bottom surface and the side walls. The plasma contains inert gas and hydrogen.

A method for encapsulating an MEMS structure in a stack structure includes providing a functional wafer structure including at least partly the MEMS structure. The method includes arranging the functional wafer structure and a glass wafer in the stack structure and along a stacking direction and is performed such that a cavity, in which at least part of the MEMS structure is arranged, is closed on one side along the stacking direction by the glass wafer and such that a spacing structure is arranged between the part of the MEMS structure and the glass wafer in the stack structure to provide a spacing between the part of the MEMS structure and the glass wafer along the stacking direction, such that the spacing structure encloses part of the cavity.

A method for manufacturing semiconductor structure includes: providing a substrate having a first surface; forming a trench on the first surface, wherein a bottom surface and side walls of the substrate are configured along an outer periphery of the trench; annealing the substrate with high-purity argon or high-purity hydrogen to flatten the bottom surface and the side walls; conformally disposing a composite-material layer to cover the first surface, the bottom surface and the side walls; disposing a polysilicon material layer in the trench; removing the composite-material layer on the first surface; forming a multi-layer metal interconnection structure on the first surface and the polysilicon material layer, the multi-layer metal interconnection structure including a MEMS frame structure and through holes; removing the polysilicon material layer and the composite-material layer; using plasma treatment to the trench to flatten the bottom surface and the side walls. The plasma contains inert gas and hydrogen.

Disclosed herein are microelectronics package architectures having self-aligned air gaps and methods of manufacturing the same. The microelectronics packages may include first and second substrates, first and second traces, and a photosensitive material. The first trace may be attached to the first substrate and comprise a first sidewall. The second trace may be attached to the first substrate and comprise a second sidewall. The second traced may be spaced a distance from the first trace with the second sidewall facing the first sidewall. First and second portions of the photosensitive material may be attached to the first and second sidewalls, respectively. The second substrate may be attached to the first and second traces. The first and second substrates and the first and second traces may form the air gap in between the first and second traces.

In accordance with an embodiment a microelectromechanical system (MEMS) device including a substrate comprising a vertically extending through hole and a horizontally extending membrane structure covering the through hole, where the membrane structure comprises a plurality of upright nanostructures for providing a liquid repellent membrane surface. In other embodiments, certain methods are used for fabricating MEMS devices.

A manufacturing method of a semiconductor device according to an embodiment implants impurities into a central portion of a polishing target film or an outer peripheral portion of the central portion of the polishing target film to cause an impurity concentration in the outer peripheral portion of the polishing target film and an impurity concentration in the central portion thereof to be different from each other, thereby modifying a surface of the polishing target film. The modified surface of the polishing target film is polished by a CMP method.

A method for manufacturing a micromechanical device includes providing a silicon substrate having a front side and a rear side, where a first normal of the front side deviates by a first angle from the <111> direction of the silicon substrate; forming in the front side first and second trenches that are spaced apart from and essentially parallel to each other, with the first and second trenches extending along a direction of the deviation; forming on the front side a first etching mask that covers the front side except for a first opening area between the first and second trenches; and anisotropically etching the front side using the etching mask, thereby forming in the opening area an oblique surface having a second angle to the first normal, which approximately corresponds to the first angle.

A manufacturing method of a semiconductor device according to an embodiment implants impurities into a central portion of a polishing target film or an outer peripheral portion of the central portion of the polishing target film to cause an impurity concentration in the outer peripheral portion of the polishing target film and an impurity concentration in the central portion thereof to be different from each other, thereby modifying a surface of the polishing target film. The modified surface of the polishing target film is polished by a CMP method.

According to one embodiment, an electronic device includes a base region, an element portion located on the base region, the element portion including a movable portion, and a protective film overlying the element portion and forming a cavity on an inner side of the protective film. The protective film includes a first protective layer and a second protective layer located on the first protective layer. A hole extends in a direction parallel to a main surface of the base region, and the second protective layer covers the hole.