Disclosed is a system for maintaining a pretreatment bath containing a pretreatment comprising a Group IVB metal. The system comprises an aqueous reducing agent comprising a metal cation and a latent source of sulfate which, upon reaction with a contaminant in the pretreatment bath, forms a metal sulfate. The contaminant comprises a nitrite source. The metal sulfate salt has a pKsp of 4.5 to 11 at a temperature of 25° C. Also disclosed is a method for maintaining a pretreatment bath containing a pretreatment composition comprising a Group IVB metal. The method comprises supplying the reducing agent to the pretreatment bath in an amount sufficient to reduce a pollution ratio of the pretreatment bath to less than 1:1. Also disclosed are substrates with a pretreatment bath maintained according to the system and method.

A bearing component includes a black-oxide layer having metallic additional elements integrated in the structure of the black-oxide layer. Also a method of forming such a black-oxide layer that includes immersing the bearing component in a bath having the metallic additional element prior to immersing the bearing component in a black oxidation solution.

A bearing component includes a black-oxide layer having metallic additional elements integrated in the structure of the black-oxide layer. Also a method of forming such a black-oxide layer that includes immersing the bearing component in a bath having the metallic additional element prior to immersing the bearing component in a black oxidation solution.

Exemplary deposition methods may include delivering a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include delivering a dopant-containing precursor with the boron-containing precursor. The dopant-containing precursor may include a metal. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a doped-boron material on a substrate disposed within the processing region of the semiconductor processing chamber. The doped-boron material may include greater than or about 80 at. % of boron in the doped-boron material.

Exemplary deposition methods may include delivering a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include delivering a dopant-containing precursor with the boron-containing precursor. The dopant-containing precursor may include a metal. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a doped-boron material on a substrate disposed within the processing region of the semiconductor processing chamber. The doped-boron material may include greater than or about 80 at. % of boron in the doped-boron material.

A method for depositing zinc on the surfaces of a coolant loop of a nuclear power plant includes: providing within a portion of the coolant loop a treatment solution comprising zinc and optionally one or more noble metals and/or reducing agent(s); allowing the treatment solution to remain in the portion for a treatment period; and removing the treatment solution from the portion. According to various embodiments, an average temperature of the treatment solution over the course of the treatment period is less than 150° C. or 100° C. According to various embodiments, an instantaneous temperature of the treatment solution remains below 150° C. or 100° C. throughout the treatment period. The zinc deposition treatment may be applied (1) before the plant is first put into power-generating operation or (2) during an outage following power-generating operation and optionally following a chemical decontamination to remove any oxides formed on surfaces of a coolant loop during prior power operation period(s).

The preset invention has as its object the provision of a laminate free of hexavalent chromium and excellent in corrosion resistance and wear resistance, and a manufacturing process of the laminate. To solve the above-described problems, a laminate according to the present invention includes a substrate, and a laminated film portion with metal films laminated in two or more layers. The laminate has an interface layer between each two adjacent ones of the metal films. The laminated film portion contains a first metal element as a principal component, the first metal element being at least one element of Ni, Cr, Co, and W, and a second metal element that is a metal element of smaller cohesive energy than that of the first metal element. The second metal element contained in the interface layer is at a content ratio higher than that of the second metal element contained in each of the adjacent metal films.

The preset invention has as its object the provision of a laminate free of hexavalent chromium and excellent in corrosion resistance and wear resistance, and a manufacturing process of the laminate. To solve the above-described problems, a laminate according to the present invention includes a substrate, and a laminated film portion with metal films laminated in two or more layers. The laminate has an interface layer between each two adjacent ones of the metal films. The laminated film portion contains a first metal element as a principal component, the first metal element being at least one element of Ni, Cr, Co, and W, and a second metal element that is a metal element of smaller cohesive energy than that of the first metal element. The second metal element contained in the interface layer is at a content ratio higher than that of the second metal element contained in each of the adjacent metal films.

Methods of patterning semiconductor devices comprising selective deposition methods are described. A blocking layer is deposited on a metal surface of a semiconductor device before deposition of a dielectric material on a dielectric surface. Methods include exposing a substrate surface including a metal surface and a dielectric surface to a heterocyclic reactant comprising a headgroup and a tailgroup in a processing chamber and selectively depositing the heterocyclic reactant on the metal surface to form a passivation layer, wherein the heterocyclic headgroup selectively reacts and binds to the metal surface.

Methods of patterning semiconductor devices comprising selective deposition methods are described. A blocking layer is deposited on a metal surface of a semiconductor device before deposition of a dielectric material on a dielectric surface. Methods include exposing a substrate surface including a metal surface and a dielectric surface to a heterocyclic reactant comprising a headgroup and a tailgroup in a processing chamber and selectively depositing the heterocyclic reactant on the metal surface to form a passivation layer, wherein the heterocyclic headgroup selectively reacts and binds to the metal surface.