G01B2210/56

Wafer inspection apparatus and method

A thickness estimating apparatus includes a transfer robot, a light source, a camera, a memory and a controller. The memory stores a thickness predicting model generated based on a data set including a thickness of at least one of a test wafer corresponding to the wafer or a test element layer formed on the test wafer, and the thickness predicting model being trained to minimize a loss function of the data set. The controller applies pixel data, which is acquired from at least one pixel selected from a plurality of pixels included in a captured image, to the thickness predicting model, to predict a thickness of at least one of the wafer or an element layer formed on the wafer in a position corresponding to a position of the selected pixel.

Wafer inspection system including a laser triangulation sensor

One example of an inspection system includes a laser, a magnification changer, and a first camera. The laser projects a line onto a wafer to be inspected. The magnification changer includes a plurality of selectable lenses of different magnification. The first camera images the line projected onto the wafer and outputs three-dimensional line data indicating the height of features of the wafer. Each lens of the magnification changer provides the same nominal focal plane position of the first camera with respect to the wafer.

Chamber for vibrational and environmental isolation of thin wafers

Measurement cavities described herein include a cylindrical chamber having a first open end and a second open end; a first cap covering the first open end of the cylindrical chamber and a second cap covering the second open end of the cylindrical chamber, wherein the first and second caps hermetically seal the cylindrical chamber and wherein the first cap is rigidly coupled to the second cap; and a wafer holder positioned within and coupled to the cylindrical chamber. The measurement cavity has a mass m, a stiffness k, and a damping constant c configured such that the transmissibility .Math. x F .Math.
of an input force at 60 Hz in the measurement cavity is reduced by a factor of at least 10 and the measurement cavity has a natural frequency of greater than 300 Hz.

Pattern Measurement Apparatus and Flaw Inspection Apparatus

The purpose of the present invention is to provide a pattern measurement apparatus that appropriately assesses patterns formed by patterning methods for forming patterns that do not exist on photomasks. In order to achieve this purpose, the present invention provides a pattern measurement apparatus comprising a processor that measures the dimensions of patterns formed on a sample by using data acquired by irradiating the sample with a beam, wherein the processor extracts pattern coordinate information on the basis of the data acquired by irradiating the sample with a beam, and uses the coordinate information to generate measurement reference data used when performing dimension measurements of the pattern.

Single Cell In-Die Metrology Targets and Measurement Methods
20230005777 · 2023-01-05 ·

Metrology targets and methods are provided, which comprise at least two overlapping structures configured to be measurable in a mutually exclusive manner at least at two different corresponding optical conditions. The targets may be single cell targets which are measured at different optical conditions which enable independent measurements of the different layers of the target. Accordingly, the targets may be designed to be very small, and be located in-die for providing accurate metrology measured of complex devices.

Wafer backside engineering for wafer stress control

A semiconductor structure and a method for managing semiconductor wafer stress are disclosed. The semiconductor structure includes a semiconductor wafer, a first stress layer disposed on and in contact with a backside of the semiconductor wafer, and a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second layer exerts a second stress on the semiconductor wafer that is opposite the first backside stress. The method includes forming a first stress layer on and in contact with a backside of a semiconductor wafer, and further forming a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second stress layer exerts a second stress on the semiconductor wafer that is opposite to the first stress.

Method and system for measuring a surface of an object comprising different structures using low coherence interferometry

A method for measuring a surface of an object including at least one structure using low coherence optical interferometry, the method including the steps of acquiring an interferometric signal at a plurality of measurement points in a field of view and, for at least one measurement point, attributing the interferometric signal acquired to a class of interferometric signals from a plurality of classes, each of the classes being associated with a reference interferometric signal representative of a typical structure; and analysing the interferometric signal to derive therefrom an item of information on the structure at the measurement point, as a function of its class.

INTEGRATED SUBSTRATE MEASUREMENT SYSTEM

An apparatus includes a substrate holder, a first actuator to rotate the substrate holder, a second actuator to move the substrate holder linearly, a first sensor to generate one or more first measurements or images of the substrate, a second sensor to generate one or more second measurements of target positions on the substrate, and a processing device. The processing device estimates a position of the substrate on the substrate holder and causes the first actuator to rotate the substrate holder about a first axis. The rotation causes an offset between a field of view of the second sensor and a target position on the substrate due to the substrate not being centered on the substrate holder. The processing device causes the second actuator to move the substrate holder linearly along a second axis to correct the offset. The processing device determines a profile across a surface of the substrate based on the one or more second measurements of the target positions.

COMBINING PHYSICAL MODELING AND MACINE LEARNING
20230023634 · 2023-01-26 · ·

A system and methods for OCD metrology are provided including receiving reference parameters, receiving multiple sets of measured scatterometric data, and receiving an optical model designed to generate one or more sets of model scatterometric data according to a set of pattern parameters, and training a machine learning model by applying, during the training, target features including the reference parameters, and by applying input features including the sets of measured scatterometric data and the sets of model scatterometric data, such that the trained machine learning model estimates new wafer pattern parameters from subsequently sets of measured scatterometric data.

Systems and methods for semiconductor chip surface topography metrology

Embodiments of systems and methods for measuring a surface topography of a semiconductor chip are disclosed. In an example, a method for measuring a surface topography of a semiconductor chip is disclosed. A plurality of interference signals and a plurality of spectrum signals are received by at least one processor. Each of the interference signals and spectrum signals corresponds to a respective one of a plurality of positions on a surface of the semiconductor chip. The spectrum signals are classified by the at least one processor into a plurality of categories using a model. Each of the categories corresponds to a region having a same material on the surface of the semiconductor chip. A surface height offset between a surface baseline and at least one of the categories is determined by the at least one processor based, at least in part, on a calibration signal associated with the region corresponding to the at least one of the categories. The surface topography of the semiconductor chip is characterized by the at least one processor based, at least in part, on the surface height offset and the interference signals.