A layer arrangement for a phased array antenna comprises phase shifting units arranged between stacked dielectric layers with a tunable dielectric material sandwiched in-between. Each phase shifting unit comprises a transmission line with phase shifting capabilities that is electrically connected with bias lines to a biasing circuit. A dielectric layer is made from an optically transparent material. An overlapping section of the bias lines of each of the phase shifting units is made from an optically transparent and electroconductive material. The tunable dielectric material affects the transmission or reflection of light that illuminates the tunable dielectric material depending on the respective tuning state. Testing this layer arrangement comprises illuminating the layer arrangement by light while a predetermined electric bias potential is applied to at least some of the phase shifting units, and during which the light emission from the layer arrangement is detected and compared with an expected light emission.

The present subject matter describes fault detection during power swing in a power transmission system. Voltage and current measurements are obtained for each phase at a terminal of the power transmission system. Based on measurements obtained, a value of change in an impedance angle for each phase-to-ground loop and each phase-to-phase loop for each sampled value of voltage and current is calculated, where the value of change in the impedance angle is a difference between impedance angles of two samples separated by a predetermined interval. Further, the average values for change in impedance angle based on a predetermined number of values of the change in the impedance angle for each phase-to-ground loop and each phase-to-phase loop is calculated. The average values calculated are compared with a threshold of change in impedance angle and based on the comparison a fault in one or more of the phase-to-ground loops or phase-to-phase loops is detected and classified.

A measurement apparatus comprising a first terminal to receive an input signal of a circuit under test; a second terminal to receive an output signal of the circuit under test. A first and second phase splitter configured to generate a first and second phase signal, I1 and I2, and a first and second quadrature signal, Q1 and Q2. A first and second multiplexer, each coupled to the first terminal and the second terminal and configured to alternately pass the input and output signals of the circuit under test to the inputs of the first and second phase splitters. A double-quadrature mixer having four inputs configured to receive I1, Q1, I2, and Q2, and an output. A calculation unit to determine one or both of a phase shift of the circuit under test and/or a gain of the circuit under test based on the output of the double-quadrature mixer.

A measurement apparatus comprising a first terminal to receive an input signal of a circuit under test; a second terminal to receive an output signal of the circuit under test. A first and second phase splitter configured to generate a first and second phase signal, I1 and I2, and a first and second quadrature signal, Q1 and Q2. A first and second multiplexer, each coupled to the first terminal and the second terminal and configured to alternately pass the input and output signals of the circuit under test to the inputs of the first and second phase splitters. A double-quadrature mixer having four inputs configured to receive I1, Q1, I2, and Q2, and an output. A calculation unit to determine one or both of a phase shift of the circuit under test and/or a gain of the circuit under test based on the output of the double-quadrature mixer.

Methods and apparatus for processing a substrate are provided herein. For example, apparatus can include a first voltage/current (V/I) probe configured to connect to an input side of a matching network of the processing chamber and a second V/I probe configured to connect to an output side of the matching network and a processor coupled to the first V/I probe and the second V/I probe and configured to, based on a phase gap between a V and I of an RF signal detected by at least one of the first V/I probe or the second V/I probe at a target frequency, detect a minimum phase gap between the V and I, and control at least one of impedance tuning of the matching network or process control of the processing chamber using at least one of a peak or RMS of V, I and phase measured at the target frequency or under sweeping frequency.

Methods and apparatus for processing a substrate are provided herein. For example, apparatus can include a first voltage/current (V/I) probe configured to connect to an input side of a matching network of the processing chamber and a second V/I probe configured to connect to an output side of the matching network and a processor coupled to the first V/I probe and the second V/I probe and configured to, based on a phase gap between a V and I of an RF signal detected by at least one of the first V/I probe or the second V/I probe at a target frequency, detect a minimum phase gap between the V and I, and control at least one of impedance tuning of the matching network or process control of the processing chamber using at least one of a peak or RMS of V, I and phase measured at the target frequency or under sweeping frequency.

Techniques for estimating a phase relation between a first binary signal and a second binary signal, in particular to a clock-to-data phase detection in double-data-rate signals. The binary signals may include both rising and falling signal edges. Techniques may include determining a first and second signal edge for the first binary signal and comparing the signal edges of the first binary signal to one or more signal edges of the second binary signal, then performing one or more calculations based on the comparisons. The phase relation between the first binary signal and the second binary signal may be determined based on the one or more calculations.

A measurement apparatus comprising a first terminal to receive an input signal of a circuit under test; a second terminal to receive an output signal of the circuit under test. A first and second phase splitter configured to generate a first and second phase signal, I1 and I2, and a first and second quadrature signal, Q1 and Q2. A first and second multiplexer, each coupled to the first terminal and the second terminal and configured to alternately pass the input and output signals of the circuit under test to the inputs of the first and second phase splitters. A double-quadrature mixer having four inputs configured to receive I1, Q1, I2, and Q2, and an output. A calculation unit to determine one or both of a phase shift of the circuit under test and/or a gain of the circuit under test based on the output of the double-quadrature mixer.

The method for detecting the phase (Φ1) of an analog signal (SA1) via a hybrid coupler (CH1) operating in a power-combiner mode, the hybrid coupler (CH1) comprising a first input (BE1) intended to receive the analog signal (SA1), a second input (BE2) intended to receive a reference signal (SREF) having a reference phase (Φ2) and the same frequency (FREF) as the analog signal (SA1), and two outputs (BS1, BS2), and configured to generate, at these two outputs (BS1, BS2), a first output signal (SS1) and a second output signal (SS2), respectively, comprises measuring peak values (A1, A2, A3, A4) of the analog signal (SA1), of the reference signal (SREF), and of at least one of the first and second output signals (SS1, SS2), calculating the phase shift (Φ1-Φ2) between the phase (Φ1) of the analog signal and the reference phase (Φ2) depending on said measured peak values (A1, A2, A3, A4), and determining the phase (Φ1) of the analog signal (SA1) depending on said calculated phase shift (Φ1-Φ2) and the reference phase (Φ2).

In one embodiment, a phase detection circuit includes a current signal input to receive a current signal indicative of a current amplitude of an RF signal and a voltage signal input to receive a voltage signal indicative of a voltage amplitude of the RF signal. A high-pass filter and a low-pass filter are each configured to filter one of (i) the current signal from the current signal input or (ii) the voltage signal from the voltage signal input, wherein the high-pass filter and the low-pass filter collectively cause a substantially 90 degree offset between a phase angle of the current signal and a phase angle of the voltage signal. A phase difference circuit receives the filtered current signal and the filtered voltage signal to determine a phase angle difference between the current signal and the voltage signal.