A die sorter tool may include a first conveyor, and a first lane to receive, from one or more load ports and via the first conveyor, a carrier with a set of dies. The die sorter tool may include a die flip module to receive the carrier from the first lane, manipulate one or more dies of the set of dies by changing orientations of the one or more dies, and return the one or more dies to the carrier after manipulating the one or more dies and without changing positions of the one or more dies within the carrier. The die sorter tool may include a second conveyor, and a second lane to receive, via the second conveyor, the carrier from the die flip module, and provide, via the first conveyor, the carrier to the one or more load ports.

A method for analyzing device test data includes accessing a core analytics rule that is based on manufacturing data of a plurality of devices. Each of the plurality of devices are produced in one of a plurality of manufacturing facilities and are of a same type as a first device being tested on a tester. The method also includes receiving initial test results of a plurality of other devices of a same type tested at a testing facility, generating, based on the initial test results, an edge analytics rule, modifying the core analytics rule based on the edge analytics rule, wherein the modified core analytics rule including modified binning limits, applying the modified core analytics rule to testing data obtained by testing the first device, and determining, based on applying the modified core analytics rule, that the first device is an outlier with respect to the modified binning limits.

A method for analyzing device test data includes accessing a core analytics rule that is based on manufacturing data of a plurality of devices. Each of the plurality of devices are produced in one of a plurality of manufacturing facilities and are of a same type as a first device being tested on a tester. The method also includes receiving initial test results of a plurality of other devices of a same type tested at a testing facility, generating, based on the initial test results, an edge analytics rule, modifying the core analytics rule based on the edge analytics rule, wherein the modified core analytics rule including modified binning limits, applying the modified core analytics rule to testing data obtained by testing the first device, and determining, based on applying the modified core analytics rule, that the first device is an outlier with respect to the modified binning limits.

A device and a method for monitoring and analysis utilize unintended electromagnetic emissions of electrically powered components, devices or systems. The emissions are received at the antenna and a receiver. A processor processes and measures change or changes in a signature of the unintended electromagnetic emissions. The measurement are analyzed to both record a baseline score for future measurements and to be used in determining status and/or health of the analyzed system or component.

A current measurement apparatus comprises: a capacitor connected in parallel to a signal terminal of a device under test (DUT); a test pattern generation apparatus generating a test pattern to operate the DUT; and a measurement module connected to one end of the capacitor. The measurement module comprises: an input/output (I/O) buffer increasing or reducing an amount of charges of the capacitor and outputting a signal corresponding to an output logic value according to a voltage of the one end of the capacitor; a time measurer measuring an arrival time which it takes for the voltage of the one end of the capacitor to reach a second voltage from a first voltage; and a controller controlling the i/o buffer and the time measurer to measure the arrival time and controlling such that a value of a current related to an inspection of a DUT is measured using the arrival time.

In accordance with one embodiment, a method for testing a plurality of electronic components is provided, including subdividing the plurality of electronic components into a plurality of first groups and subdividing the plurality of electronic components into a plurality of second groups. The method may further include measuring, for each first group, an electrical parameter of an interconnection of the components of the first group; measuring, for each second group, an electrical parameter of an interconnection of the components of the second group, and determining which electronic components of the plurality of electronic components have a predefined property, on the basis of the result of the measurement of the electrical parameter for the first groups and on the basis of the result of the measurement of the electrical parameter for the second groups.

A method, system and computer program product, the method comprising: obtaining circuit information, comprising description of groups of pins of electronic chips; obtaining a description of a test comprising a plurality of rules specifying: an identifier, a first group of pins, a second group of pins, a first action to take upon successful interconnection of the first and second groups, and a second action to take upon failure, wherein the first action and second actions are one of: finish with success, finish with failure, and a rule ID of a subsequent rule to check; checking the plurality of rules, comprising checking a sequence of rules starting with a first rule, and wherein each subsequent rule is selected as the first or second action of a preceding rule, in accordance with whether the preceding rule succeeded or failed, respectively; and outputting a result of the plurality of rules.

An Apparatus and Method for reliably sorting RFID chips, in inlays, labels, tags or other units of manufacture, into rows and columns, and using that information to report their exact position on a moving web, in support of further manufacturing processes, in the presence of crosstalk, with speed and accuracy exceeding prior art.

A semiconductor integrated circuit test system can include a first semiconductor integrated circuit tester configured to conduct a first test of a first characteristic of one of a plurality of semiconductor integrated circuits, wherein the first test is completed by the first semiconductor integrated circuit tester within a first test time. A second semiconductor integrated circuit tester, can be coupled to the first semiconductor integrated circuit tester, where the second semiconductor integrated circuit tester can be configured to conduct a second test of a second characteristic of each of the plurality of the semiconductor integrated circuits simultaneously, wherein the second test is completed within a second test time that is at least about two orders of magnitude more than the first test time.

A semiconductor integrated circuit test system can include a first semiconductor integrated circuit tester configured to conduct a first test of a first characteristic of one of a plurality of semiconductor integrated circuits, wherein the first test is completed by the first semiconductor integrated circuit tester within a first test time. A second semiconductor integrated circuit tester, can be coupled to the first semiconductor integrated circuit tester, where the second semiconductor integrated circuit tester can be configured to conduct a second test of a second characteristic of each of the plurality of the semiconductor integrated circuits simultaneously, wherein the second test is completed within a second test time that is at least about two orders of magnitude more than the first test time.