Patent classifications
G01R31/01
Multi-flip semiconductor die sorter tool
A die sorter tool may include a first conveyor, and a first lane to receive, from one or more load ports and via the first conveyor, a carrier with a set of dies. The die sorter tool may include a die flip module to receive the carrier from the first lane, manipulate one or more dies of the set of dies by changing orientations of the one or more dies, and return the one or more dies to the carrier after manipulating the one or more dies and without changing positions of the one or more dies within the carrier. The die sorter tool may include a second conveyor, and a second lane to receive, via the second conveyor, the carrier from the die flip module, and provide, via the first conveyor, the carrier to the one or more load ports.
Multi-flip semiconductor die sorter tool
A die sorter tool may include a first conveyor, and a first lane to receive, from one or more load ports and via the first conveyor, a carrier with a set of dies. The die sorter tool may include a die flip module to receive the carrier from the first lane, manipulate one or more dies of the set of dies by changing orientations of the one or more dies, and return the one or more dies to the carrier after manipulating the one or more dies and without changing positions of the one or more dies within the carrier. The die sorter tool may include a second conveyor, and a second lane to receive, via the second conveyor, the carrier from the die flip module, and provide, via the first conveyor, the carrier to the one or more load ports.
Pulsed high current technique for characterization of device under test
A test and measurement circuit including a capacitor in parallel with a device under test, a direct current voltage source configured to charge the capacitor, a pulse generator configured to generate a pulse for testing the device under test, and a sensor for determining a current in the device under test.
Method and apparatus for monitoring capacitor faults in a capacitor bank
A method and an apparatus are presented which enable the identification of a capacitor fault in a given string of a capacitor bank, based on the computation of the string impedance by measuring the string AC current and voltages, where each string includes a plurality of capacitor elements connected in series. The method consists of measuring the string capacitive impedance and comparing this value with a previously measured capacitive impedance of the same string. If a difference between these two values is obtained, which exceeds a given threshold for a certain duration, a fault is recorded.
Multilayer ceramic capacitor having ultra-broadband performance
The present invention is directed to a multilayer ceramic capacitor that includes a plurality of active electrodes and at least one shield electrode that are each arranged within a monolithic body and parallel with a longitudinal direction. The capacitor may exhibit a first insertion loss value at a test frequency, which may be greater than about 2 GHz, in a first orientation relative to the mounting surface. The capacitor may exhibit a second insertion loss value at about the test frequency in a second orientation relative to the mounting surface and the capacitor is rotated 90 degrees or more about the longitudinal direction with respect to the first orientation. The longitudinal direction of the capacitor may be parallel with the mounting surface in each of the first and second orientations. The second insertion loss value may differ from the first insertion loss value by at least about 0.3 dB.
Methods and apparatus to improve detection of capacitors implemented for regulators
An apparatus includes a resistor having a resistor terminal. The apparatus includes a capacitor coupled to the resistor terminal. The apparatus includes a transistor having a current terminal and a gate. The gate is coupled to the resistor terminal and coupled to the capacitor. The apparatus includes a comparator having a comparator input and a comparator output. The comparator input is coupled to the current terminal. The apparatus includes a latch having a latch input coupled to the comparator output.
Multilayer Ceramic Capacitor Having Ultra-Broadband Performance
The present invention is directed to a multilayer ceramic capacitor that includes a plurality of active electrodes and at least one shield electrode that are each arranged within a monolithic body and parallel with a longitudinal direction. The capacitor may exhibit a first insertion loss value at a test frequency, which may be greater than about 2 GHz, in a first orientation relative to the mounting surface. The capacitor may exhibit a second insertion loss value at about the test frequency in a second orientation relative to the mounting surface and the capacitor is rotated 90 degrees or more about the longitudinal direction with respect to the first orientation. The longitudinal direction of the capacitor may be parallel with the mounting surface in each of the first and second orientations. The second insertion loss value may differ from the first insertion loss value by at least about 0.3 dB.
METHOD FOR CONFECTIONING RESISTORS, RESISTOR, AND HEATING DEVICE
This disclosure refers to a method for confectioning resistors that each comprise a PTC ceramic plate and metallic electrode layers covering opposite faces of the ceramic plate, said method comprising the following steps: measuring an electrical resistance of a resistor to be confectioned by applying an electrical potential to one of electrode layers such that an electric current flows from one of the electrode layers through the ceramic plate to the electrode layer on the opposite face of the ceramic plate, comparing the measured resistance to a target resistance, and removing, if the measured resistance is lower than the target resistance, a section of at least one of the electrode layers. This disclosure also refers to such a resistor and a heating device comprising such resistors.
SYSTEMS AND METHODS FOR MULTIDIMENSIONAL DYNAMIC PART AVERAGE TESTING
Embodiments of the present invention provide systems and methods for multidimensional parts average testing for testing devices and analyzing testing results to detect outliers according to embodiments of the present invention. The testing can include calculating multivariate (e.g., bivariate) statistics using delta measurements of like devices, a ratio of measurements, or principal component analysis that identifies eigenvectors and eigenvalues to define meta parameters, for example. Raw test result data can be converted to residual space and robust regression can be performed to prevent outlier results from influencing regression, thereby reducing overkill advantageously.
MULTI-FLIP SEMICONDUCTOR DIE SORTER TOOL
A die sorter tool may include a first conveyor, and a first lane to receive, from one or more load ports and via the first conveyor, a carrier with a set of dies. The die sorter tool may include a die flip module to receive the carrier from the first lane, manipulate one or more dies of the set of dies by changing orientations of the one or more dies, and return the one or more dies to the carrier after manipulating the one or more dies and without changing positions of the one or more dies within the carrier. The die sorter tool may include a second conveyor, and a second lane to receive, via the second conveyor, the carrier from the die flip module, and provide, via the first conveyor, the carrier to the one or more load ports.