[Object] To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area of a surface electrode or increasing the number of semiconductor devices (number of chips) to be obtained from one wafer, and a method for manufacturing the same.

[Solution Means] A semiconductor device 1 includes an n-type SiC layer 2 having a first surface 2A, a second surface 2B, and end faces 2C, a p-type voltage relaxing layer 7 formed in the SiC layer 2 so as to be exposed to the end portion of the first surface 2A of the SiC layer 2, an insulating layer 8 formed on the SiC layer 2 so as to cover the voltage relaxing layer 7, and an anode electrode 9 that is connected to the first surface 2A of the SiC layer 2 through the insulating layer 8 and has a pad area 95 selectively exposed.

The present application relates to a test circuit, comprising: M test units, each test unit having a first terminal and a second terminal, a first terminal of each test unit being connected to a power wire, a second terminal of each test unit being connected to a ground wire, M being a positive integer; each test unit comprises a TDDB test component, a switch, and a control circuit; the TDDB test component has a first equivalent resistance before being broken down, the TDDB test component has a second equivalent resistance after being broken down, and the first equivalent resistance is greater than the second equivalent resistance.

An electrostatic discharge and electrical overstress detection circuit includes protection circuit, sensing circuit, clamp circuit, several stages of sampling logic circuits connected in sequence and storage circuit. Protection circuit is coupled between input/output pin and internal chip and discharges to a power supply terminal when the electrostatic discharge or electrical overstress events happen. Sensing circuit and clamp circuit are coupled between power supply terminal and ground terminal. Each stage of sampling logic circuit is coupled to power supply terminal and memory cell of storage circuit, and the first stage of sampling logic is coupled to the clamp circuit, and when the electrostatic discharge or electrical overstress events happen, the several stages of sampling logic circuits sample voltage of the power supply terminal one by one and change state of corresponding memory cell, so that the electrostatic discharge or electrical overstress events are successively recorded by the memory cell.

A method for detecting a series arc in a photovoltaic device, operating in direct current mode, including N (N=1 or N>1) photovoltaic modules, connected to a charging device having a capacitive behavior for the modules, the method including: a) detecting, across n of the N modules (1≦n≦N), time evolution of voltage; b) identifying a voltage variation between a first zone of stable voltage and a second zone of stable voltage for a duration of at least 5 μs, which immediately follows the voltage variation; and c) determining whether the voltage variation is between a value Vmin higher than or equal to 0.2 V and a value Vmax lower than or equal to 20 V, with rise time of the variation between a duration Tmin higher than or equal to 0.5 μs and a duration Tmax lower than or equal to 5 μs.

A handler for holding an electronic device during high voltage testing includes conductive lead guides for shorting leads on one side of the isolator together and connectors connecting the lead guides to conductors.

Disclosed herein is a method of detecting an arc generated in a semiconductor device. The method may comprise: performing a processing process for a substrate processing and collecting data according to the processing process; separating the collected data by setting sections; obtaining an average value and a standard deviation of the data separated for each section; and setting an upper limit and a lower limit for detecting the arc using the average value and the standard deviation.

A method of estimating a breakdown voltage of a silicon dioxide film includes; generating breakdown voltage information associated with first test dies selected from among test dies, generating a breakdown voltage estimation model by updating a parameter of a neural network model based on the breakdown voltage information, applying test voltages to second test die selected from among the test dies and distinct from the first dies and receiving currents levels for current generated by the second test dies in response to the test voltages, wherein the test voltages have respective levels lower than levels of breakdown voltages for the first test dies, and estimating breakdown voltages of the second test dies using the breakdown voltage estimation model in relation to the currents levels.

A method of manufacturing a semiconductor package includes covering a semiconductor die and a plurality of conductive terminals coupled to the semiconductor die in a mold compound, positioning the mold compound between a first pair of electrodes and a second pair of electrodes, and moving a movable electrode of the first pair and a movable electrode of the second pair into a first clamping position. In the first clamping position, each of the first pair of electrodes and the second pair of electrodes electrically couples to a unique subset of the plurality of conductive terminals. The method also includes applying, by the first pair of electrodes, a first voltage to the semiconductor die within the mold compound; and applying, by the second pair of electrodes, a second voltage to the semiconductor die within the mold compound. The second voltage is less than the first voltage.

A time dependent dielectric breakdown test structure includes a plurality of test units connected in parallel between a constant voltage and a ground. Each of the plurality of test units includes a dielectric test sample connected to the constant voltage; and a current restraint unit connected between the dielectric test sample and the ground, for restraining a breakdown current from flowing on the dielectric test sample after the constant voltage has broken the dielectric test sample.

An electromagnetic wave detector includes a semiconductor layer, a two-dimensional material layer, a first electrode portion, a second electrode portion, and a ferroelectric layer. Two-dimensional material layer is electrically connected to semiconductor layer. First electrode portion is electrically connected to two-dimensional material layer. Second electrode portion is electrically connected to two-dimensional material layer with semiconductor layer interposed therebetween. Ferroelectric layer is electrically connected to at least any one of first electrode portion, second electrode portion and semiconductor layer. Electromagnetic wave detector is configured such that an electric field generated from ferroelectric layer is shielded with respect to two-dimensional material layer. Alternatively, ferroelectric layer is arranged so as not to be overlapped with two-dimensional material layer in plan view.