The embodiments of the present disclosure provide a semiconductor base plate and a test method thereof. When a first test line and a second test line in the semiconductor base plate are tested, a resistivity of the first test line can be tested by directly loading voltages to a first test pad and a second test pad after a first conductive layer is formed and before a first insulating layer is formed. After a second conductive layer is formed, a resistivity of the second test line is tested by loading voltages to a third test pad and a fourth test pad.

Probe cards for probing highly-scaled integrated circuits are provided. A probe card includes a backplane and an array of probes extending from the backplane. Each of the probes includes a cantilever member and a probe tip. A first end of the cantilever member is coupled to the backplane, such that the cantilever member extends from the backplane. The probe tip extends from a second end of the cantilever member. The probes are fabricated from semiconductor materials. Each probe is configured to transmit electrical signals between the backplane and a device under test (DUT), via corresponding electrodes of the DUT. The probes are highly-scaled such that the feature size and pitch of the probes matches the highly-scaled feature size and pitch of the DUT's electrodes. The probes comprise atomic force microscopy (AFM) probes that are enhanced for increased electrical conductivity, elasticity, lifetime, and reliability.

Enhanced probe cards, for testing unpackaged semiconductor die including numerous discrete devices (e.g., LEDs), are described. The die includes anodes and cathodes for the LEDs. Via a single touchdown event, the probe card may simultaneously operate each of the LEDs. The LEDs' optical output is measured and the performance of the die is characterized. The probe card includes a conductive first contact and another contact that are fabricated from a conformal sheet or film. Upon the touchdown event, the first contact makes contact with each of the die's anodes and the other contact makes contact with each of the die's cathodes. The vertical and sheet resistance of the contacts are sufficient such that the voltage drop across the vertical dimension of the contacts is approximately an order of magnitude greater than the operating voltage of the LEDs and current-sharing between adjacent LEDs is limited by the sheet resistance.

A fault diagnosis device is configured to diagnose a fault in a light emitting unit that emits light of a color according to an operating state of a robot by individually energizing and lighting a plurality of types of LEDs of different emission colors. The fault diagnosis device includes an energization control unit that controls energization of the LEDs, a voltage detection unit that detects a diagnostic voltage that varies depending on a terminal voltage of the LEDs, and a fault detection unit that detects a fault in the light emitting unit based on a control state of energization by the energization control unit and a detected value of the diagnostic voltage by the voltage detection unit.

An inspection apparatus includes a light sensor that detects light from a semiconductor device to which an electric signal has been input, an optical system that guides light from the semiconductor device to the light sensor, and a control device electrically connected to the light sensor. The control device includes a measurement unit that acquires waveform data obtained by optical measurement for each of a plurality of positions on a defective semiconductor device and waveform data obtained by the optical measurement for each of a plurality of positions on a non-defective semiconductor device, a calculation unit that calculates a degree of correspondence between the waveform data of the defective semiconductor device and the waveform data of the non-defective semiconductor device, and an analysis unit that analyzes a defective part of the defective semiconductor device on the basis of the degree of correspondence for each of the plurality of positions.

The invention discloses a method and a system for correction of the junction temperatures of an IGBT module in a photovoltaic inverter. The method includes: constructing an electrothermal coupling model of an IGBT model based on a photovoltaic inverter topology, a light radiation intensity, and an ambient temperature; selecting an IGBT collector-emitter on-state voltage drop as an aging parameter and designing an on-state voltage drop sampling circuit to ensure measurement accuracy; constructing an aging database for IGBT modules in different aging stages based on large current and small current injection methods; comparing a junction temperature value output by the electrothermal coupling model with the calibrated junction temperature value and calibrating an aging process coefficient of an electrothermal coupling model correction formula; comparing an IGBT aging monitoring value with the aging threshold to determine the aging process and selecting a corresponding aging process coefficient to ensure accuracy of junction temperature data.

The invention discloses a method and a system for correction of the junction temperatures of an IGBT module in a photovoltaic inverter. The method includes: constructing an electrothermal coupling model of an IGBT model based on a photovoltaic inverter topology, a light radiation intensity, and an ambient temperature; selecting an IGBT collector-emitter on-state voltage drop as an aging parameter and designing an on-state voltage drop sampling circuit to ensure measurement accuracy; constructing an aging database for IGBT modules in different aging stages based on large current and small current injection methods; comparing a junction temperature value output by the electrothermal coupling model with the calibrated junction temperature value and calibrating an aging process coefficient of an electrothermal coupling model correction formula; comparing an IGBT aging monitoring value with the aging threshold to determine the aging process and selecting a corresponding aging process coefficient to ensure accuracy of junction temperature data.

A testing probe system includes probes configured to contact shared probe pads of multi-channel die of a wafer; and a controller configured to generate testing patterns and receive signals from the multi-channel die of the wafer. The controller is configured to contact a probe of the probes with a shared probe pad of the multi-channel die, select a first channel of the multi-channel die to test, select at least one test mode for testing the first channel, stimulate at least the first channel during a single contact period, acquiring a first output of the first channel during the single contact period, select a second channel of the multi-channel die to test, select at least one test mode for testing the second channel, stimulate at least the second channel during the single contact period, and acquire a second output of the first channel during the single contact period.

A testing probe system includes probes configured to contact shared probe pads of multi-channel die of a wafer; and a controller configured to generate testing patterns and receive signals from the multi-channel die of the wafer. The controller is configured to contact a probe of the probes with a shared probe pad of the multi-channel die, select a first channel of the multi-channel die to test, select at least one test mode for testing the first channel, stimulate at least the first channel during a single contact period, acquiring a first output of the first channel during the single contact period, select a second channel of the multi-channel die to test, select at least one test mode for testing the second channel, stimulate at least the second channel during the single contact period, and acquire a second output of the first channel during the single contact period.

A substrate support includes a supporting unit and a light irradiation mechanism. The supporting unit includes a plate member on which an inspection target is placed and a transparent member. The light irradiation mechanism is configured to irradiate light to increase a temperature of the inspection target. Each of the plate member and the transparent member is made of a low thermal expansion material having a linear expansion coefficient of 1.0×10.sup.−6/K or less.