A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.

An embodiment of a method for operating a modular test bench is disclosed, wherein the modular test bench comprises at least one test module to test a test object. The method comprises receiving first information on a hardware revision and on a software revision of the test module and receiving second information on a hardware revision and on a software revision of the test object. The method further comprises determining, if the combination of the first information and the second information fulfills a predetermined criterion and outputting a check signal, enabling the use of the test bench if the combination of the first information and the second information fulfills the predetermined criterion.

Damage to a joint part of a terminal of an electronic component mounted on a substrate is detected. The substrate includes a base material unit, a land, and a light detection unit. The land included in the substrate is arranged with a stress light emitting body configured to emit light in accordance with stress, includes a transparent member, and is joined with a terminal of an element arranged in the base material unit included in the substrate. The light detection unit included in the substrate is arranged between the base material unit and the land included in the substrate, and detects light from the stress light emitting body.

A method for aligning a device includes: loading devices sequentially on an upper surface of a base plate having vacuum holes; suctioning the loaded device with vacuum pressure that allows minute movement of the loaded device, as the vacuum pressure is applied while the device is loaded on the base plate; moving an alignment vision assembly positioned above the base plate to the upper portion of the device to be aligned and then lowering the alignment vision assembly; checking a position of the device with a vision means through a through hole and an opening in a state, in which an alignment block surrounds the device, so as to inform a controller of the coordinates of the device; and aligning the device by finely moving the base plate in X-Y-θ directions according to the coordinates so that the device is guided to two surfaces of the opening.

A temperature adjusting device including a main body and a pressing component is provided. The main body includes a first main body thru-hole and a second main body thru-hole. The main body has a first fluid channel and a second fluid channel therein, the first fluid channel is in spatial communication with the first main body thru-hole, and the second fluid channel is in spatial communication with the second main body thru-hole. The pressing component partially protrudes from one side of the main body, the pressing component has a fluid accommodating slot therein that is in spatial communication with the first fluid channel and the second fluid channel. A fluid having a predetermined temperature can enter into the main body from the first main body thru-hole, enter into the fluid accommodating slot through the first fluid channel, and exit the main body through the second main body thru-hole.

Provided is a measurement apparatus including a signal source configured to output a binary digital signal configuring a multi-tone waveform, a waveform acquisition unit configured to acquire an analog signal waveform generated in response to application of the digital signal to a device under test, and a computation unit configured to calculate a frequency characteristic of the device under test from the waveform acquired by the waveform acquisition unit, in which the signal source is configured to repeatedly output a signal upconverted by multiplying a pseudo-random binary sequence (PRBS) signal by a repeating rectangular wave with a reference frequency and a reference duty ratio.

A chip testing apparatus including a chip testing machine, a temperature testing device, and a lid is provided. The chip testing machine includes a substrate and a plurality of chip testing sockets. Each of the chip testing sockets is disposed on the substrate and configured to carry a chip under test. The temperature adjusting device is disposed on the chip testing machine, and the lid covers the temperature adjusting device and the chip testing sockets. The temperature adjusting device includes a main body and a plurality of pressing components. The main body includes a plurality of fluid channels, and each of the pressing components can press one side of one of the chips under test. A fluid can flow into one of the fluid channels and flow through the pressing components, so that the chips under test are in an environment having a predetermined temperature.

An apparatus and a method for inspecting a semiconductor includes a water tank which includes a housing, an interior of which is filled with a liquid, and a support block which provides a settling surface for an inspection object inside the housing. A plurality of signal generators are installed on a bottom surface of the housing, and output a frequency signal in a direction in which the inspection object is located. A power supply operates the signal generators. A probe is placed above the inspection object, and a receiver which operates with the probe and is attached to a bottom surface of the support block. Foreign matter remaining on the inspection object are removed, using a plurality of frequency signals which are output by the plurality of signal generating units.

A semiconductor integrated circuit includes: one input terminal; multiple output terminals; multiple first current control elements connected between the input terminal and the respective output terminals; a control circuit that controls the first current control elements; a fault detection circuit that includes multiple voltage comparator circuits each of which compares a voltage proportional to a voltage of one of the output terminals with a predetermined threshold voltage and that detects an open-circuit state or a short-circuit state of the output terminals; an external terminal connected to an external resistor; a voltage convertor circuit that generates the threshold voltage according to a voltage of the external terminal that is generated by flowing a current through the external resistor, the threshold voltage being applied to an input terminal of each of the voltage comparator circuits; and a detection result output terminal for outputting a detection result by the fault detection circuit.

A socket assembly with liquid cooling frame for a semiconductor integrated circuit (IC) chip is provided. The socket assembly includes a liquid cooling socket frame including a metallic frame body defining an opening sized to receive the semiconductor IC chip, wherein the frame body includes one or more channels transversely positioned through the frame body and positioned in an interior of the frame body, the channels defining a fluid path. The socket assembly also includes a socket cartridge including a metallic cartridge body defining a plurality of cavities each sized to receive a test probe therein, the socket frame covering a portion of the socket cartridge and exposing the plurality of cavities at the opening.