A photonic structure is provided. The photonic structure includes a first oxide layer in a semiconductor substrate, a second oxide layer over an upper surface of the semiconductor substrate and an upper surface of the first oxide layer, and an optical coupling region over an upper surface of the second oxide layer. The optical coupling region is made of silicon, and an area of the optical coupling region is confined within an area of the first oxide layer in a plan view.

Methods for patterning of multi-depth layers for the fabrication of optical devices are provided. In one embodiment, a method is provided that includes disposing a resist layer over a device layer disposed over a top surface of a substrate, the device layer having a first portion and a second portion, patterning the resist layer to form a first resist layer pattern having a plurality of first openings and a second resist layer pattern having a plurality of second openings, and etching exposed portions of the device layer defined by the plurality of first openings and the plurality of second openings, wherein the plurality of first openings are configured to form at least a portion of a plurality of first structures within the optical device, and the plurality of second openings are configured to form at least a portion of a plurality of second structures within the optical device.

The invention relates to a process for fabricating an optoelectronic system (1) comprising an optical device (60) coupled to an integrated photonic circuit (20), comprising producing a lower waveguide (13.1) from the thin single-crystal-silicon layer (13) of a first SOI substrate (10), then joining a second SOI substrate (40) thereto and producing an intermediate waveguide (43.1) from the thin single-crystal-silicon layer (43) of the second SOI substrate (40).

In some embodiments, the present disclosure relates to a device having a first waveguide and a second waveguide arranged over a substrate. The first waveguide has a first input terminal and a first output terminal, wherein the first input terminal is configured to receive light. The second waveguide is arranged laterally beside the first waveguide and has a second input terminal and a second output terminal. The second input terminal of the second waveguide is configured to receive light. The first waveguide further includes a first portion that has a different structure than surrounding portions of the first waveguide. The second waveguide further includes a second portion that has a different structure than surrounding portions of the second waveguide. The first waveguide is spaced apart at a maximum distance from the second waveguide at the first portion and the second portion.

Photonic packages and device assemblies that include photonic integrated circuits (PICs) coupled to optical lenses on lateral sides of the PICs. An example photonic package comprises a package support, an integrated circuit (IC), an insulating material, a PIC having an active side and a lateral side substantially perpendicular to the active side. At least one optical structure is on the active side. A substantial portion of the active side is in contact with the insulating material, and the PIC is electrically coupled to the package support and to the IC. The photonic package further includes an optical lens coupled to the PIC on the lateral side. In some embodiments, the photonic package further includes an interposer between the PIC or the IC and the package support.

A waveguide platform and method of fabricating a waveguide platform on a silicon wafer; the method comprising: providing a wafer having a layer of crystalline silicon;

lithographically defining a first region of the top layer; electrochemically etching the wave-guide platform to create porous silicon at the lithographically defined first region; epitaxially growing crystalline silicon on top of the porous silicon to create a first upper crystalline layer with a first buried porous silicon region underneath; wherein the first buried porous silicon region defines a taper between a first waveguide region of crystalline silicon having a first depth and a second waveguide region of crystalline silicon having a second depth which is smaller than the first depth.

Embodiments disclosed herein include electronic packages with photonics integrated circuits (PICs). In an embodiment, an electronic package comprises a glass substrate with a first recess and a second recess. In an embodiment, a PIC is in the first recess. In an embodiment, an optics module is in the second recess, and an optical waveguide is embedded in the glass substrate between the first recess and the second recess. In an embodiment, the optical waveguide optically couples the PIC to the optics module.

A method includes defining a first waveguide in a first region of an optical device over a first dielectric layer over a silicon on insulator (SOI) substrate of the optical device and disposing a second dielectric layer on the first waveguide and the first dielectric layer of the optical device. The method also includes defining a second region on the second dielectric layer, the first dielectric layer, and the SOI substrate. The second region includes an integrated trench structure defined in the SOI substrate. The method further includes etching the second region to form an etched second region, disposing a third dielectric layer in the etched second region, and disposing a second waveguide on at least the third dielectric layer. The second waveguide is disposed to provide an optical coupling between the second waveguide and the first waveguide.

A photonic module, comprising a first waveguide; a second waveguide, disposed on an opposing side of the first waveguide to a substrate; and, a coupling section. One of the first waveguide and the second waveguide is formed of crystalline silicon. The other of the first waveguide and the second waveguide is formed of amorphous silicon. The coupling section is configured to couple light between the first waveguide and the second waveguide. Such a silicon photonic module has enhanced coupling and transmission properties in contrast to conventional modules.

A method of making a photonic integrated circuit (PIC) is provided. The method comprises depositing a functional resist material layer over a substrate, disposing and pressing a stamp with a plurality of nanopatterns into the functional resist material for a period of time, and removing the stamp from the functional resist material to provide nanofeatures that are inverted versions of the nanopatterns, wherein the nanofeatures form one or more optical elements.