A wavelength division multiplexing filter comprises: a first multi-order Mach-Zehnder interferometer comprising a plurality of first-order Mach-Zehnder interferometers, and a second multi-order Mach-Zehnder interferometer comprising a plurality of first-order Mach-Zehnder interferometers; wherein the first multi-order Mach-Zehnder interferometer and the second multi-order Mach-Zehnder interferometer are included in a group of multiple multi-order Mach-Zehnder interferometers arranged within a binary tree arrangement, the binary tree arrangement comprising: a first set of a plurality of multi-order Mach-Zehnder interferometers, the first set including the first multi-order Mach-Zehnder interferometer, and having an associated spectral response with a first spacing between adjacent passbands, and a second set of at least twice as many multi-order Mach-Zehnder interferometers as in the first set, the second set including the second multi-order Mach-Zehnder interferometer, and having an associated spectral response with a second spacing between adjacent passbands that is twice the first spacing.

A Mach-Zehnder interferometer (MZI) filter comprising one or more passive compensation structures are described. The passive compensation structures yield MZI filters that are intrinsically tolerant to perturbations in waveguide dimensions and/or other ambient conditions. The use of n+1 waveguide widths can mitigate n different sources of perturbation to the filter. The use of at least three different waveguide widths for each Mach-Zehnder waveguide can alleviate sensitivity of filter performance to random width or temperature variations. A tolerance compensation portion is positioned between a first coupler section and a second coupler section, wherein the tolerance compensation portion includes a first compensation section having a second width, a second compensation section having a third width and a third compensation section having a fourth width, wherein the fourth width is greater than the third width and the third width is greater than the second width.

The present invention relates to a photonic chip carried out by the combination and interconnection of equally-oriented Programmable Photonics Processing Blocks, with all their longitudinal axes in parallel, implemented over a photonic chip that is capable of implementing one or multiple, simultaneous photonics circuits with optical feedback paths and/or linear multiport transformations, by the appropriate programming of its resources and the selection of its input and output ports. The invention also relates to a parallel field-programmable photonic array (P-FPPA) comprising of, at least one programmable circuit based on equally-oriented/parallel tunable beam-splitters with independent coupling and phase-shifting configuration and peripheral high-performance building blocks.

In an optical transmitter having an electro-optic modulator with first child MZI and a second child MZI nested to form a parent MZI, and a processor that controls the bias voltages of electro-optic modulator. In the first section of a control loop, the processor simultaneously superimposes different dither signals onto the first bias voltage of the first child MZI and 1.0 the second bias voltage of the second child MZI, and extracts the first phase error information for the first child MZI and the first-round third phase error for the parent MZI from a first monitoring result. In the second section of the control loop, the processor simultaneously superimposes different dither signals onto the first and second bias voltages, and extracts the second phase error information for the second child MZI and the second-round third phase error for the parent MZI from a second monitoring result.

Structures for a photonics chip, testing methods for a photonics chip, and methods of forming a structure for a photonics chip. A photonics chip includes a first waveguide, a second waveguide, an optical tap coupling the first waveguide to the second waveguide, and a photodetector coupled to the second waveguide. A laser is attached to the photonics chip. The laser is configured to generate laser light directed by the first waveguide to the optical tap.

An optical device is disclosed, including a phase delay, a first adiabatic coupler adapted to receive an input signal and adapted to be optically coupled to an input of the phase delay, and a second adiabatic coupler adapted to be optically coupled to an output of the phase delay. The second adiabatic coupler includes a first waveguide including a first portion optically coupled to the first output and including a first width, and a second waveguide including a second portion optically coupled to the second output and including a second width that is approximately equal to the first width.

An integrated circuit includes an electronic circuit. The integrated circuit further includes a photonic device. The photonic device includes a first photodetector (PD) electrically connected to the electronic circuit. The photonic device further includes a second PD electrically connected to the electronic circuit. The photonic device further includes a first waveguide configured to receive an optical signal input, wherein the first waveguide is optically connected to the first PD. The photonic device further includes a second waveguide optically connected to the second PD. The photonic device further includes a resonant structure between the first waveguide and the second waveguide, wherein the resonant structure is configured to optically couple the first waveguide to the second waveguide.

A system for parallel photonic computation, preferably including a source module, a plurality of input modulator units, an optical interference unit (OIU), and a plurality of detector banks. An OIU, preferably including one or more unitary matrix modules and optionally including a diagonal matrix module. An input modulator, which can include one or more waveguides, couplers, and/or modulator banks. A method for parallel photonic computing, preferably including encoding input vectors, performing a desired matrix operation, and receiving output values, and optionally including performing electronic computations and/or performing further optical computations based on the outputs, which can function to compute the results of a matrix operation on many different input vectors in parallel.

Configurations for a light splitting device used for light splitting over an operating bandwidth of wavelengths are disclosed. The light splitting device may include a first coupler and a second coupler, where the first coupler has a first splitting power relationship and the second coupler has a second splitting power relationship and the first and second splitting power relationships are complementary to one another over the operating bandwidth of wavelengths. The light splitting device may further include a phase delay positioned between the first and second couplers. The phase delay may result in the output light having an approximately even optical power distribution across the operating bandwidth of wavelengths. In some embodiments, the first and second couplers may be directional couplers and, in other embodiments, the first and second couplers may be tapered couplers.

An eyepiece includes a substrate and an in-coupling grating patterned on a single side of the substrate. A first grating coupler is patterned on the single side of the substrate and has a first grating pattern. The first grating coupler is optically coupled to the in-coupling grating. A second grating coupler is patterned on the single side of the substrate adjacent to the first grating coupler. The second grating coupler has a second grating pattern different from the first grating pattern. The second grating coupler is optically coupled to the in-coupling grating.