Provided are an array substrate and a manufacturing method thereof, and a display device. The array substrate comprises a plurality of data lines and sub-pixels. At least one sub-pixel comprises: a first insulating layer; a gate; an active layer located on one side of the first insulating layer away from the gate; a pixel electrode; a first electrode located connected to the active layer and in contact with the pixel electrode; a second electrode connected to the active layer and a data line; a second insulating layer having a first opening, wherein the orthographic projection of the first opening partially overlaps with the orthographic projections of the pixel electrode and the first electrode; a connection electrode in contact with the pixel electrode and the first electrode through the first opening; and a common electrode located on one side of the second insulating layer away from the pixel electrode.

An array substrate includes: a first substrate; a plurality of gate lines and a plurality of data lines; a plurality of thin film transistors; and a plurality of reflective electrodes. The plurality of gate lines and the plurality of data lines define a plurality of sub-pixel regions. A thin film transistor is located in a sub-pixel region. A reflective electrode is located in the sub-pixel region and electrically connected to the thin film transistor in the same sub-pixel region. Each reflective electrode has a border including a plurality of first sub-borders extending in a first direction, a plurality of second sub-borders extending in a second direction, and a plurality of chamfer borders each connecting a first sub-border and a second sub-border that are adjacent; and an intersection of extension lines of the first sub-border and the second sub-border is located outside the border of the reflective electrode.

According to one embodiment, a display device includes a first substrate having a first transparent substrate and a pixel electrode, a second substrate having a second transparent substrate, a first common electrode, a second common electrode, and an insulating film disposed between the first common electrode and the second common electrode, and a liquid crystal layer. The first common electrode is disposed between the liquid crystal layer and the insulating film, and includes a first opening and a first electrode portion. The second common electrode is disposed between the insulating film and the second transparent substrate, and includes a second electrode portion overlapping the first opening.

Disclosed are a display substrate (10) and a display device. The display substrate (10) includes at least one irregularly-shaped pixel (103), and a shape of a boundary line of a side, proximal to a peripheral region (101b), of each irregularly-shaped pixel (103) matches with a shape of a boundary line (101a1) of an irregularly-shaped display region (101a) in a base substrate (101), such that the irregularly-shaped pixel (103) does not go beyond the irregularly-shaped display region (101a) of the display substrate (10), a narrow bezel of the display substrate (10) can be realized conveniently, and an image displayed at the boundary line (101a1) of the irregularly-shaped display region (101a) may be prevented from being in a zigzag shape, thereby ensuring a display effect of the display device. Moreover, because an area of an orthographic projection of the irregularly-shaped pixel (103) on the base substrate (101) is smaller than an area of an orthographic projection of a rectangular pixel (102) on the base substrate (101), an area of an opening (a) formed by a black matrix layer (104) in a region where each rectangular pixel (102) is disposed is larger than an area of an opening (b) formed by the black matrix layer (104) in a region where any irregularly-shaped pixel (103) is disposed, such that a smooth transition of luminance of light emitted by the irregularly-shaped pixel (103) and the rectangular pixel (102) can be ensured, and the luminance uniformity of the display device is better.

Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS): correcting circuits (34, 36) connected between an input terminal (IN) inputted with an input signal and control terminals (gates) of the first transistors; capacitors (C2, C3) connected between the control terminals and the input terminal; diode-connected second transistors (35, 37) that are provided between nodes (N5, N6) between the capacitors and the control terminals and the power supply potentials and have the substantially same threshold voltage as the first transistors; and switches (SW2, SW3) connected in series with the second transistors.

A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.

The present disclosure discloses an array substrate, a display device and manufacturing methods thereof. The array substrate comprises: a base, a gate metal layer, an active layer, a source/drain metal layer, and a pixel electrode layer, wherein the array substrate has a storage capacitor region; in the storage capacitor region, the gate metal layer, the active layer, the source/drain metal layer and the pixel electrode layer comprise respective patterns; wherein, the projections of the gate metal layer storage pattern, the active layer storage pattern, the source/drain metal layer storage pattern, and the pixel electrode layer storage pattern on the base at least partially overlap, and the pixel electrode layer storage pattern is electrically connected to the gate metal layer storage pattern to form a first electrode of the storage capacitor, the active layer storage pattern is electrically connected to the source/drain metal layer storage pattern to form a second electrode.

A liquid crystal display includes a first insulation substrate, a gate line, a data line configured to cross the gate line while being insulated therefrom, a thin film transistor connected to the gate line and the data line, a pixel electrode configured to include a first subpixel electrode connected to the thin film transistor and a second subpixel electrode, a second insulation substrate configured to face the first insulation substrate, a common electrode disposed on the second insulation substrate, and a liquid crystal layer disposed between the first insulation substrate and the second insulation substrate to include a plurality of liquid crystal molecules, where each of the first subpixel electrode and the second subpixel electrode includes a unit pixel electrode including a plurality of minute branches that is extended from a horizontal stem and a vertical stem.

A thin film transistor (TFT) substrate and a display device using the same are disclosed. The TFT substrate includes a first TFT including a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode deposited on a substrate, a second TFT separated from the first TFT, the second TFT including a second gate electrode, an oxide semiconductor layer, a second source electrode, and a second drain electrode deposited on the first gate electrode, and a plurality of storage capacitors separated from the first and second TFTs, each storage capacitor including a first dummy semiconductor layer, a first gate insulating layer on the first dummy semiconductor layer, a first dummy gate electrode on the first gate insulating layer, and an intermediate insulating layer on the first dummy gate electrode.

A thin-film transistor array includes an insulating substrate and pixels each including a thin-film transistor, a pixel electrode, and a capacitor electrode, the pixels being formed in a matrix and located at positions where column wirings extending in a column direction intersect row wirings perpendicular to the column wirings and extending in a row direction. The thin-film transistor includes a gate electrode, a source electrode, a drain electrode, and a semiconductor pattern formed between the source electrode and the drain electrode. The pixel electrode includes two electrically conductive layers which are a lower layer electrode serving as a lower pixel electrode, and an upper layer electrode serving as an upper pixel electrode. The corresponding one of the column wirings is at a position which has no overlap with the capacitor electrode and the lower pixel electrode, and has an overlap with the upper pixel electrode, in the lamination direction.