A method and a system for correcting lithography process hotspots based on stress damping adjustment are provided. The method includes: acquiring a mark hotspot of a mask pattern; forming N annuli centered on the mark hotspot from inner to outer on a mask; moving vertexes of the mask pattern located in each annulus by a specific distance in a direction deviating from the mark hotspot and connecting the moved vertexes according to an original connection relationship to acquire an updated layout; verifying electrical characteristics of the updated layout, determining whether a deviation of the electrical characteristics of the updated layout is within a tolerable range, and performing geometric correction to compensate for a deviation of electrical parameters if no is determined and then ending correction, or ending the correction if yes is determined.

A method and a system for correcting lithography process hotspots based on stress damping adjustment are provided. The method includes: acquiring a mark hotspot of a mask pattern; forming N annuli centered on the mark hotspot from inner to outer on a mask; moving vertexes of the mask pattern located in each annulus by a specific distance in a direction deviating from the mark hotspot and connecting the moved vertexes according to an original connection relationship to acquire an updated layout; verifying electrical characteristics of the updated layout, determining whether a deviation of the electrical characteristics of the updated layout is within a tolerable range, and performing geometric correction to compensate for a deviation of electrical parameters if no is determined and then ending correction, or ending the correction if yes is determined.

A method for determining a patterning device pattern. The method includes obtaining (i) an initial patterning device pattern having at least one feature, and (ii) a desired feature size of the at least one feature, obtaining, based on a patterning process model, the initial patterning device pattern and a target pattern for a substrate, a difference value between a predicted pattern of the substrate image by the initial patterning device and the target pattern for the substrate, determining a penalty value related the manufacturability of the at least one feature, wherein the penalty value varies as a function of the size of the at least one feature, and determining the patterning device pattern based on the initial patterning device pattern and the desired feature size such that a sum of the difference value and the penalty value is reduced.

A method of determining a mask pattern for a target pattern to be printed on a substrate. The method includes partitioning a portion of a design layout including the target pattern into a plurality of cells with reference to a given location on the target pattern; assigning a plurality of variables within a particular cell of the plurality of cells, the particular cell including the target pattern or a portion thereof; and determining, based on values of the plurality of variables, the mask pattern for the target pattern such that a performance metric of a patterning process utilizing the mask pattern is within a desired performance range.

A method of manufacturing a semiconductor device includes forming M_1st segments in a first metallization layer including: forming first and second M_1st segments for which corresponding long axes extend in a first direction and are substantially collinear, the first and second M_1st segments being free from another instance of M_1st segment being between the first and second M_1st segments; and (A) where the first and second M_1st segments are designated for corresponding voltage values having a difference equal to or less than a reference value, separating the first and second M_1st segments by a first gap; or (B) where the first and second M_1st segments are designated for corresponding voltage values having a difference greater than the reference value, separating the first and second M_1st segments by a second gap, a second size of the second gap being greater than a first size of the first gap.

A method of manufacturing a semiconductor device includes forming M_1st segments in a first metallization layer including: forming first and second M_1st segments for which corresponding long axes extend in a first direction and are substantially collinear, the first and second M_1st segments being free from another instance of M_1st segment being between the first and second M_1st segments; and (A) where the first and second M_1st segments are designated for corresponding voltage values having a difference equal to or less than a reference value, separating the first and second M_1st segments by a first gap; or (B) where the first and second M_1st segments are designated for corresponding voltage values having a difference greater than the reference value, separating the first and second M_1st segments by a second gap, a second size of the second gap being greater than a first size of the first gap.

A lithography process is described by a design for a lithographic mask and a description of the lithography configuration, which may include the lithography source, collection/illumination optics, projection optics, resist, and/or subsequent fabrication steps. The actual lithography process uses a lithographic mask fabricated from the mask design, which may be different than the nominal mask design. A mask fabrication model models the process for fabricating the lithographic mask from the mask design. Typically, this is an electron-beam (e-beam) process, which includes e-beam exposure of resist on a mask blank, processing of the exposed resist to form patterned resist, and etching of the mask blank with the patterned resist. The mask fabrication model, usually in conjunction with other process models, is used to estimate a result of the lithography process. Mask correction is then applied to the mask design based on the simulation result.

A lithography process is described by a design for a lithographic mask and a description of the lithography configuration, which may include the lithography source, collection/illumination optics, projection optics, resist, and/or subsequent fabrication steps. The actual lithography process uses a lithographic mask fabricated from the mask design, which may be different than the nominal mask design. A mask fabrication model models the process for fabricating the lithographic mask from the mask design. Typically, this is an electron-beam (e-beam) process, which includes e-beam exposure of resist on a mask blank, processing of the exposed resist to form patterned resist, and etching of the mask blank with the patterned resist. The mask fabrication model, usually in conjunction with other process models, is used to estimate a result of the lithography process. Mask correction is then applied to the mask design based on the simulation result.

Enhancing target features of a pattern imaged onto a substrate. This may include adding one or more assist features to a patterning device pattern in one or more locations adjacent to one or more target features in the patterning device pattern. The one or more assist features are added based on two or more different focus positions in the substrate. This can also include shifting the patterning device pattern and/or a design layout based on the two or more different focus positions and the one or more added assist features. This may be useful for improving across slit asymmetry. Adding the one or more assist features to the pattern and shifting the pattern and/or the design layout enhances the target features by reducing a shift caused by across slit asymmetry for a slit of a multifocal lithographic imaging apparatus. This may reduce the shift across an entire imaging field.

An optical proximity correction method includes designing a mask design. The designing of the mask design includes setting a reference point of the mask design, calculating a plurality of chief ray angles of a plurality of points of interest on the mask design, respectively, each of the plurality of points of interest having a corresponding distance from the reference point, finding, among the plurality of points of interest, a first point of interest having a maximum chief ray angle among the plurality of chief ray angles, a distance of the first point of interest from the reference point being set as a deteriorated distance, and compensating for distortion of an image to be transferred from a pattern located at the deteriorated distance from the reference point of the mask design.