A memory device is provided. The memory device includes a main feature disposed beneath a surface of a photolithographic mask. The memory device further includes at least one Sub-Resolution Assistant Feature (SRAF) proximate to the main feature beneath the surface. The main feature has an electrical conductivity based on an area relationship with the at least one SRAF.

A memory device is provided. The memory device includes a main feature disposed beneath a surface of a photolithographic mask. The memory device further includes at least one Sub-Resolution Assistant Feature (SRAF) proximate to the main feature beneath the surface. The main feature has an electrical conductivity based on an area relationship with the at least one SRAF.

The present disclosure relates to a system and method for designating, for a hologram, a color to be implemented, by forming a certain pattern on a dithering mask, such that a hologram structure may express a particular structural color. To this end, the present disclosure may include an image obtaining unit configured to obtain an original image; an encryption unit configured to convert original colors of respective pixels included in the original image into encrypted colors, according to a predefined standard; a pattern data generation unit configured to generate, based on the encrypted colors, pattern data including dithering patterns corresponding to the respective pixels; and a pattern forming unit configured to form, based on the pattern data, a mask pattern on a dithering mask.

The present disclosure relates to a system and method for designating, for a hologram, a color to be implemented, by forming a certain pattern on a dithering mask, such that a hologram structure may express a particular structural color. To this end, the present disclosure may include an image obtaining unit configured to obtain an original image; an encryption unit configured to convert original colors of respective pixels included in the original image into encrypted colors, according to a predefined standard; a pattern data generation unit configured to generate, based on the encrypted colors, pattern data including dithering patterns corresponding to the respective pixels; and a pattern forming unit configured to form, based on the pattern data, a mask pattern on a dithering mask.

In semiconductor devices requiring the formation of fully depleted SOI transistor elements in combination with non-FET elements, such as substrate diodes and the like, the patterning of the active regions may be accomplished on the basis of deep isolation trenches, which may be formed first on the basis of immersion-based lithography, followed by formation of shallow isolation trenches also formed on the basis of immersion lithography. Thereafter, respective openings connecting to the substrate materials may be formed, possibly in combination with isolation trenches of reduced depth compared to the deep isolation trenches, on the basis of non-immersion lithography techniques. In this manner, device scaling for semiconductor devices requiring critical dimensions of 26 nm and less in a planar transistor architecture may be accomplished.

In semiconductor devices requiring the formation of fully depleted SOI transistor elements in combination with non-FET elements, such as substrate diodes and the like, the patterning of the active regions may be accomplished on the basis of deep isolation trenches, which may be formed first on the basis of immersion-based lithography, followed by formation of shallow isolation trenches also formed on the basis of immersion lithography. Thereafter, respective openings connecting to the substrate materials may be formed, possibly in combination with isolation trenches of reduced depth compared to the deep isolation trenches, on the basis of non-immersion lithography techniques. In this manner, device scaling for semiconductor devices requiring critical dimensions of 26 nm and less in a planar transistor architecture may be accomplished.

A memory device is provided. The memory device includes a main feature disposed beneath a surface of a photolithographic mask. The memory device further includes at least one Sub-Resolution Assistant Feature (SRAF) proximate to the main feature beneath the surface. The main feature has an electrical conductivity based on an area relationship with the at least one SRAF.

A memory device is provided. The memory device includes a main feature disposed beneath a surface of a photolithographic mask. The memory device further includes at least one Sub-Resolution Assistant Feature (SRAF) proximate to the main feature beneath the surface. The main feature has an electrical conductivity based on an area relationship with the at least one SRAF.

Embodiments of the invention relate to methods and apparatus useful in the nanopatterning of large area substrates, where a rotatable mask is used to image a radiation-sensitive material. Typically the rotatable mask comprises a cylinder. The nanopatterning technique makes use of Near-Field photolithography, where the mask used to pattern the substrate is in contact or close proximity with the substrate. The Near-Field photolithography may make use of an elastomeric phase-shifting mask, or may employ surface plasmon technology, where a rotating cylinder surface comprises metal nano holes or nanoparticles.