The device for accurate measurement of time intervals comprises a first comparator (1) to the input of which a first signal (STA) is fed and the output of which is connected to the first of the inputs of the combiner (3), to the second input of which the output of a second comparator (2) is connected, to the input of which a second signal (STO) is fed. The output of the combiner (3) is connected to the input of an analogue filter (4), the output of which is connected to the input of an analogue-to-digital converter (5), the output of which is connected to the input of a control and signal processing circuit (6), to the second input of which a reference clock signal (REF) is further fed, which is simultaneously fed to another input of the analogue-to-digital converter (5) and the output of the control and signal processing circuit (6) is a data output (DAT) of time intervals.

The device for accurate measurement of time intervals comprises a first comparator (1) to the input of which a first signal (STA) is fed and the output of which is connected to the first of the inputs of the combiner (3), to the second input of which the output of a second comparator (2) is connected, to the input of which a second signal (STO) is fed. The output of the combiner (3) is connected to the input of an analogue filter (4), the output of which is connected to the input of an analogue-to-digital converter (5), the output of which is connected to the input of a control and signal processing circuit (6), to the second input of which a reference clock signal (REF) is further fed, which is simultaneously fed to another input of the analogue-to-digital converter (5) and the output of the control and signal processing circuit (6) is a data output (DAT) of time intervals.

A time measurement device measures a time interval between input timings of first and second pulsed target signals. The device includes: a processor; a number-of-periods detector that detects, by using a clock signal with a predetermined clock frequency and a predetermined clock period, the time interval in units of the clock period; and a phase detection unit including a band-pass filter. The band-pass filter receives at least one of the first and second target signals as a filtering target signal and extracts a signal component of the clock frequency from the filtering target signal. The phase detection unit detects a phase difference between the extracted signal and the clock signal. The processor derives, by using a result detected by the number-of-periods detector and the detected phase difference, the time interval at a resolution finer than the clock period.

A time measurement device measures a time interval between input timings of first and second pulsed target signals. The device includes: a processor; a number-of-periods detector that detects, by using a clock signal with a predetermined clock frequency and a predetermined clock period, the time interval in units of the clock period; and a phase detection unit including a band-pass filter. The band-pass filter receives at least one of the first and second target signals as a filtering target signal and extracts a signal component of the clock frequency from the filtering target signal. The phase detection unit detects a phase difference between the extracted signal and the clock signal. The processor derives, by using a result detected by the number-of-periods detector and the detected phase difference, the time interval at a resolution finer than the clock period.

A delay circuit with multiple dependencies on various environmental parameters is disclosed. The delay circuit is configured to receive an input signal. The delay circuit includes a first circuit configured to generate a first amount of delay, wherein the first amount of delay has a direct relationship to a first environmental parameter. The delay circuit also includes a second circuit configured to generate a second amount of delay such that the second amount of delay has an inverse relationship to a second environmental parameter. The delay circuit is configured to generate a delayed output signal based on the first and second amounts of delay generated by the first and second circuits.

A delay circuit with multiple dependencies on various environmental parameters is disclosed. The delay circuit is configured to receive an input signal. The delay circuit includes a first circuit configured to generate a first amount of delay, wherein the first amount of delay has a direct relationship to a first environmental parameter. The delay circuit also includes a second circuit configured to generate a second amount of delay such that the second amount of delay has an inverse relationship to a second environmental parameter. The delay circuit is configured to generate a delayed output signal based on the first and second amounts of delay generated by the first and second circuits.

A time measurement device for calculating a time from an input of a first trigger signal to an input of a second trigger signal as a measured time includes a start gate configured to generate a start signal, a stop gate configured to generate a stop signal, a TDC circuit configured to generate a digital code corresponding to the time from an input of a start signal to an input of a stop signal, a delay circuit configured to delay an input of at least one of the start signal and the stop signal to the TDC circuit by a predetermined delay time, and a control unit configured to calculate a measured time on the basis of a plurality of digital codes generated by the TDC circuit, wherein the time delay unit selects at least two delay times.

A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.

A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.

A delay time detection circuit includes below configurations. A clock generation unit generates a sub scale clock signal, based on a system clock signal. A count unit generates a count signal while sequentially and repeatedly incrementing a count number, based on the sub scale clock signal. A sub scale signal generation unit receives the count signal, and generates sub scale signals, equal in number to the count number, that each have, at a rate of once in the count number, a rectangular wave for a duration being associated with a second period and that are shifted in timing relative to one another according to the second period. A delay time calculation unit receives the input clock signal, and calculates a delay time within a range of the first period of the input clock signal with respect to the system clock signal, based on one of the sub scale signals.