Patent classifications
G05B2219/13119
AUTOMATION CODE GENERATOR FOR INTEROPERABILITY ACROSS INDUSTRIAL ECOSYSTEMS
Current approaches to integrating industrial ecosystems, for instance integrating automation functions across different vendors, lack efficiencies and capabilities. For example, system integrators are often required to develop special software that functions as a proxy or adaptor between different systems. In such cases, the proxy or adaptor is often specific to a particular set of equipment or vendors, and which can limit reusability, among other technical drawbacks. Embodiments described herein overcome e one or more of the described-herein shortcomings or technical problems by providing methods, systems, and apparatuses for automatically generating interfaces, for instance glue code, that enables interoperability between different ecosystems in automated industrial systems.
Method for Configuring an Industrial Automation Component, Industrial Automation Component, Computer Program and Computer Readable Medium
An industrial automation component, a computer program and a computer-readable medium and method for configuring an industrial automation component, wherein at least one feature of the industrial automation component that is not configurable with an engineering system supporting the component, non-supported feature, is configured by interpreting a description of a configuration of the at least one non-supported feature with an on-board compiler of the component and integrating the interpreted description to a basic configuration having been generated with the engineering system and with respect to at least one further feature, supported feature, of the component.
Compiler and programming support device
A non-transitory computer readable-medium storing a compiler to cause a computer to perform processing for compiling sequence programs including a declaration of a global variable and generating an execution program to be executed by a PLC. When there is a change in a memory address in the PLC assigned to the global variable between before and after edit of a declaration of the global variable, the compiler gives an execution code to synchronize a first value stored at a memory address assigned to an unedited global variable with a second value stored at a memory address assigned to an edited global variable to an execution program corresponding to the sequence program that references the edited global variable.
COMPILER AND PROGRAMMING SUPPORT DEVICE
A non-transitory computer readable-medium storing a compiler to cause a computer to perform processing for compiling sequence programs including a declaration of a global variable and generating an execution program to be executed by a PLC. When there is a change in a memory address in the PLC assigned to the global variable between before and after edit of a declaration of the global variable, the compiler gives an execution code to synchronize a first value stored at a memory address assigned to an unedited global variable with a second value stored at a memory address assigned to an edited global variable to an execution program corresponding to the sequence program that references the edited global variable.
Method of optimally compiling PLC command
Disclosed embodiments include a system and a method of compiling a PLC (Programmable Logic Controller) command. In some embodiments, the method includes: determining one compile processing scheme chosen from a plurality of compile processing schemes for a command included in a program to be executed in a PLC; and executing a command compile or compiler optimized for a rate or a size based on the chosen compile processing scheme.
METHOD OF OPTIMALLY COMPILING PLC COMMAND
Disclosed embodiments include a system and a method of compiling a PLC (Programmable Logic Controller) command. In some embodiments, the method includes: determining one compile processing scheme chosen from a plurality of compile processing schemes for a command included in a program to be executed in a PLC; and executing a command compile or compiler optimized for a rate or a size based on the chosen compile processing scheme.
Compiler for neural accelerator
A compiler of a computing device is described that identifies a sequence of neural network models frequently invoked by an application of the computing device, compiles the models in that sequence, and loads a static random access memory (SRAM) of a hardware accelerator with the compiled models only when the same compiled modelsfrom another, but same, sequence that was previously invokedare not already present in the SRAM. This prevents unnecessary reloading of compiled models into the SRAM, thereby increasing runtime speed and conserving computational energy.