An electromagnetic immunity test system includes a data acquisition and control device, a linear module, an electromagnetic disturbance simulator, and an upper computer. The data acquisition and control device is in a data connection to the linear module, the electromagnetic disturbance simulator, and the upper computer. The linear module includes a grating ruler; and the linear module is disposed on the numerical control machine tool to measure location data of the sliding table of the numerical control machine tool and transmit the location data to the data acquisition and control device. The electromagnetic disturbance simulator is configured to generate and transmit an electromagnetic signal to the numerical control system. The data acquisition and control device is configured to read the location data in real time and transfer the real-time location data to the upper computer.

A multiplex device including a multiplex connecting section connected to a movable side multiplex device, the multiplex connecting section being configured to transmit a position signal outputted from a position signal output section connected to the movable side multiplex device by multiplexing communication with the movable side multiplex device; an amplifier connecting section connected to a position signal output section amplifier, the amplifier being configured to transmit the position signal to the position signal output section amplifier; a measuring device connecting section connected to a position signal measuring device; and a switching section configured to switch from a connection between the multiplex connecting section and the position signal output section amplifier, and a connection between the multiplex connecting section and the position signal measuring device in accordance with detection of a connection between the measuring device connecting section and the position signal measuring device.

A data processing method for safe Instrumentation and Control Systems (I&C Systems) based on data processing in safety I&C Systems consisting of self-diagnosable modules of the platform with the unified architecture, to use specifically developed computing facilities implemented in FPGA, to design and configure the modules with the unified architecture of the unified units, to use units operation in different clock domains and diversity technologies, to design and configure the computing facilities, to provide mutual diagnostics and self-diagnostics for hardware, computing facilities, interfaces and data transfer at both modular and system levels implemented by hardware design tools and module platform logic, to use different software for application diverse logic design, to provide I&C System functional safety, to simplify design of modules and I&C Systems, to provide unified process and diagnostics and self-diagnostics coverage, to simplify user operation, to simplify I&C System maintenance and support.

A data processing method for safe Instrumentation and Control Systems (I&C Systems) based on data processing in safety I&C Systems consisting of self-diagnosable modules of the platform with the unified architecture, to use specifically developed computing facilities implemented in FPGA, to design and configure the modules with the unified architecture of the unified units, to use units operation in different clock domains and diversity technologies, to design and configure the computing facilities, to provide mutual diagnostics and self-diagnostics for hardware, computing facilities, interfaces and data transfer at both modular and system levels implemented by hardware design tools and module platform logic, to use different software for application diverse logic design, to provide I&C System functional safety, to simplify design of modules and I&C Systems, to provide unified process and diagnostics and self-diagnostics coverage, to simplify user operation, to simplify I&C System maintenance and support.

Methods and apparatus relating to FPGA (Field-Programmable Gate Array) based acceleration in robot motion planning are described. In an embodiment, logic circuitry (such as an FPGA), coupled to a processor, accelerates one or more motion planning operations for a plurality of objects. A first memory, coupled to the logic circuitry, stores data corresponding to a plurality of Oriented Bounding Boxes (OBBs). The plurality of OBBs are to provide Bounding Volume (BV) models for the plurality of objects. Other embodiments are also disclosed and claimed.

Hardware accelerators are scored according to various metrics and attributes that characterize the accelerators. Examples of suitable accelerator scoring criteria include whether the software simulation of the accelerator is complete, whether hardware testing is complete, whether the accelerator is currently deployed, the number of times the accelerator has been deployed to a private cloud, the number of times the accelerator has been deployed to a public cloud, ratings by users, number of failures, number of executions, space utilization and efficiency, code metrics, power consumption, speed, and image characteristics, including space used, resources used, use of dedicated functions on a programmable device, etc. These accelerator scoring criteria are tracked for each accelerator in an accelerator scoring catalog. When an accelerator is needed, accelerator selection criteria is specified and compared with the accelerator scoring criteria in the accelerator scoring catalog to locate one or more accelerators that satisfy the accelerator selection criteria.

Methods and apparatus relating to FPGA (Field-Programmable Gate Array) based acceleration in robot motion planning are described. In an embodiment, logic circuitry (such as an FPGA), coupled to a processor, accelerates one or more motion planning operations for a plurality of objects. A first memory, coupled to the logic circuitry, stores data corresponding to a plurality of Oriented Bounding Boxes (OBBs). The plurality of OBBs are to provide Bounding Volume (BV) models for the plurality of objects. Other embodiments are also disclosed and claimed.

A data processing method for safe Instrumentation and Control Systems (I&C Systems) based on data processing in safety I&C Systems consisting of self-diagnosable modules of the platform with the unified architecture, to use specifically developed computing facilities implemented in FPGA, to design and configure the modules with the unified architecture of the unified units, to use units operation in different clock domains and diversity technologies, to design and configure the computing facilities, to provide mutual diagnostics and self-diagnostics for hardware, computing facilities, interfaces and data transfer at both modular and system levels implemented by hardware design tools and module platform logic, to use different software for application diverse logic design, to provide I&C System functional safety, to simplify design of modules and I&C Systems, to provide unified process and diagnostics and self-diagnostics coverage, to simplify user operation, to simplify I&C System maintenance and support.

A multiplex device including a multiplex connecting section connected to a movable side multiplex device, the multiplex connecting section being configured to transmit a position signal outputted from a position signal output section connected to the movable side multiplex device by multiplexing communication with the movable side multiplex device; an amplifier connecting section connected to a position signal output section amplifier, the amplifier being configured to transmit the position signal to the position signal output section amplifier; a measuring device connecting section connected to a position signal measuring device; and a switching section configured to switch from a connection between the multiplex connecting section and the position signal output section amplifier, and a connection between the multiplex connecting section and the position signal measuring device in accordance with detection of a connection between the measuring device connecting section and the position signal measuring device.

In an embodiment of the invention, an apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; a field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA; wherein the apparatus triggers a switch of an FPGA image in the FPGA to another FPGA image. In another embodiment of the invention, a method comprises: triggering, by an apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image; herein the apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; the field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA. In yet another embodiment of the invention, an article of manufacture comprises a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising: triggering, by the apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image, wherein the apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; the field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA.